公开(公告)号：US11900523B2

公开(公告)日：2024-02-13

申请号：US17505387

申请日：2021-10-19

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Michael Apodaca ,  Carson Brownlee ,  Thomas Raoux ,  Joshua Barczak ,  Gabor Liktor

IPC: G06T15/06 ,  G06T1/20

CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T2200/04

Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.

公开(公告)号：US11769288B2

公开(公告)日：2023-09-26

申请号：US17868618

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Karthik Vaidyanathan ,  Jefferson Amstutz ,  Atsuo Kuwahara ,  Michael Doyle ,  Travis Schluessler

IPC: G06T15/00 ,  G06T15/06 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T15/06 ,  G06T2210/21

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US11527035B2

公开(公告)日：2022-12-13

申请号：US17308828

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Carson Brownlee ,  Gabor Liktor ,  Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Thomas Raoux

IPC: G06T15/06 ,  G06T15/80 ,  G06T15/04

Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.

公开(公告)号：US11257274B2

公开(公告)日：2022-02-22

申请号：US16887439

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00 ,  G06F9/48 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US11210841B2

公开(公告)日：2021-12-28

申请号：US16803614

申请日：2020-02-27

Applicant: Intel Corporation

Inventor： Carsten Benthin ,  Gabor Liktor

IPC: G06T15/06 ,  G06T15/00

Abstract: An apparatus and method are described for using tessellation hardware to generate bounding volume hierarchies (BVHs) and perform other ray tracing operations. For example, one embodiment of an apparatus comprises: a shader to output a plurality of tessellation factors and one or more input surfaces; and a tessellation circuit comprising first circuitry and/or logic to tesselate each input surface to generate a new set of primitives and second circuitry and/or logic to concurrently generate a bounding volume hierarchy (BVH) 1521 based on the new set of primitives.

公开(公告)号：US11004252B2

公开(公告)日：2021-05-11

申请号：US16236245

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carson Brownlee ,  Gabor Liktor ,  Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Thomas Raoux

IPC: G06T15/06 ,  G06T15/80 ,  G06T15/04

Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.

公开(公告)号：US10957096B2

公开(公告)日：2021-03-23

申请号：US16447397

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC: G06T15/00 ,  G06T15/30 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60

Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US10832371B2

公开(公告)日：2020-11-10

申请号：US16236305

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Michael Doyle ,  Travis Schluessler ,  Gabor Liktor ,  Atsuo Kuwahara ,  Jefferson Amstutz

IPC: G06T15/10 ,  G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00 ,  G06T15/06

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US10699475B1

公开(公告)日：2020-06-30

申请号：US16235517

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Thomas Raoux ,  Carson Brownlee ,  Gabor Liktor

IPC: G06T15/40 ,  G06T15/04 ,  G06T15/00 ,  G06T15/06

Abstract: Multi-pass apparatus and method for ray tracing shading. For example, one embodiment of an apparatus comprises: graphics processing circuitry to execute a sequence of visibility testing operations related to texels within a texture domain to generate visibility results; a register or memory to store a texel mask; texel mask update circuitry/logic to update the texel mask based on the visibility results, the texel mask comprising a plurality of bits to indicate visibility of the texels within the texture domain, the texel mask update circuitry/logic to set a first bit to indicate whether any bits in the texel mask indicate a visible texel; a shader dispatcher to initiate conditional dispatch operations only if the first bit is set to indicate that at least one bit in the texel mask indicates a visible texel, wherein to perform the conditional dispatch operations, the shader dispatcher is to dispatch texel shaders for only those texels that the texel mask indicates may be visible; and a plurality of execution units (EUs) to execute the shaders dispatched by the shader dispatcher.

公开(公告)号：US20200073810A1

公开(公告)日：2020-03-05

申请号：US16566188

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0862 ,  G06F12/0875 ,  G06F9/30 ,  G06T1/20 ,  G06F9/38 ,  G06F12/0855 ,  G06F12/0811

Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.