公开(公告)号：US20190131437A1

公开(公告)日：2019-05-02

申请号：US16095655

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Van Hoang LE ,  Gilbert William DEWEY ,  Marko RADOSAVLJEVIC ,  Rafael RIOS ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L29/06 ,  H01L29/24

Abstract: Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.

公开(公告)号：US20190393223A1

公开(公告)日：2019-12-26

申请号：US16480948

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Van H. LE ,  Gilbert William DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Yih WANG ,  Shriram SHIVARAMAN

IPC: H01L27/108 ,  H01L27/13 ,  G11C11/4096 ,  G11C11/408 ,  H01L29/786 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40 ,  H01L21/311 ,  H01L49/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/24 ,  H01L29/22

Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.

公开(公告)号：US20190252020A1

公开(公告)日：2019-08-15

申请号：US16320023

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Rafael RIOS ,  Abhishek Anil SHARMA ,  Van H. LE ,  Gilbert William DEWEY ,  Jack T. KAVALIEROS

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0007 ,  G11C8/16 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1666

Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.