公开(公告)号：US09496161B2

公开(公告)日：2016-11-15

申请号：US15050387

申请日：2016-02-22

Applicant: INTEL CORPORATION

Inventor： John C. Johnson ,  Eric J. Moret ,  Lawrence M. Palanuk ,  Gregory A. Stone

IPC: H01L21/67 ,  H01L21/78 ,  H01L21/673 ,  H01L21/677 ,  H01L21/683 ,  H01L21/687 ,  H05K13/00 ,  H01L21/68

CPC classification number: H01L21/67333 ,  H01L21/67265 ,  H01L21/67309 ,  H01L21/67356 ,  H01L21/67363 ,  H01L21/67383 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67778 ,  H01L21/68 ,  H01L21/6833 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/78 ,  H05K13/0084

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract translation: 一种方法包括识别晶片上的多个管芯的晶片位置，将多个管芯中的每个管芯的晶片位置存储在数据库中，将晶片切割成多个单个管芯，将每个单模管芯定位在管芯中 在托盘上的位置位置，并将模具位置存储在数据库中的每个单个模具的托盘上。 数据库包括包括与每个模具位置相关联的晶片位置的信息。 托盘被运送到处理工具，并且多个分割模具中的至少一个从托盘上的模具位置移除并在处理工具中进行处理。 在处理之前，单独模具位于托盘上的相同的限定位置处理被处理的单个模具。 描述和要求保护其他实施例。

公开(公告)号：US09305816B2

公开(公告)日：2016-04-05

申请号：US14142761

申请日：2013-12-28

Applicant: INTEL CORPORATION

Inventor： John C. Johnson ,  Peter A. Davison ,  Eric J. Moret ,  Lawrence M. Palanuk ,  Gregory A. Stone

IPC: H01L21/67 ,  H01L21/78 ,  H01L21/677 ,  H01L21/683 ,  H01L21/687 ,  H05K13/00 ,  H01L21/673 ,  H01L21/68

CPC classification number: H01L21/67333 ,  H01L21/67265 ,  H01L21/67309 ,  H01L21/67356 ,  H01L21/67363 ,  H01L21/67383 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67778 ,  H01L21/68 ,  H01L21/6833 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/78 ,  H05K13/0084

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

公开(公告)号：US09929031B2

公开(公告)日：2018-03-27

申请号：US15295943

申请日：2016-10-17

Applicant: INTEL CORPORATION

Inventor： John C. Johnson ,  Eric J. Moret ,  Lawrence M. Palanuk ,  Gregory A. Stone

IPC: H01L21/673 ,  H01L21/78 ,  H01L21/677 ,  H01L21/683 ,  H01L21/687 ,  H05K13/00 ,  H01L21/68 ,  H01L21/67

CPC classification number: H01L21/67333 ,  H01L21/67265 ,  H01L21/67309 ,  H01L21/67356 ,  H01L21/67363 ,  H01L21/67383 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67778 ,  H01L21/68 ,  H01L21/6833 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/78 ,  H05K13/0084

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

公开(公告)号：US20250079278A1

公开(公告)日：2025-03-06

申请号：US18460406

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Karumbu Nathan Meyyappan ,  Pooya Tadayon ,  Ziyin Lin ,  Gregory A. Stone

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: In one embodiment, an apparatus comprises a substrate with conductive contacts on a first side of the substrate and a housing coupled to the first side of the substrate. The housing defines a set of holes around the conductive contacts. The apparatus further includes Gallium-based liquid metal in each hole, with the liquid metal being in contact with the conductive contact of the hole. The apparatus further includes a passivation layer on a surface of the liquid metal in each hole, the passivation layer being on an opposite end of the hole from the conductive contact in the hole.