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公开(公告)号:US20210004032A1
公开(公告)日:2021-01-07
申请号:US17031446
申请日:2020-09-24
Applicant: Intel Corporation
Inventor: Aurelien Mozipo , Archanna Srinivasan , Guang Chen , Janani Chandrasekhar
IPC: G05F1/56 , H03K19/17736 , H03K17/22
Abstract: An electronic system includes first, second, third, and fourth integrated circuit dies. The third integrated circuit die has a first voltage regulator circuit. A supply voltage output of the first voltage regulator circuit is coupled to provide a first supply voltage to a supply voltage input of the first integrated circuit die. The first voltage regulator circuit generates a first power ready signal that indicates when the first supply voltage has reached a first threshold voltage. The fourth integrated circuit die has a second voltage regulator circuit that generates a second supply voltage in response to the first power ready signal. A supply voltage output of the second voltage regulator circuit is coupled to provide the second supply voltage to a supply voltage input of the second integrated circuit die.
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2.
公开(公告)号:US20210313989A1
公开(公告)日:2021-10-07
申请号:US17353549
申请日:2021-06-21
Applicant: Intel Corporation
Inventor: Ping-Chen Liu , Guang Chen , Venu Kondapalli
IPC: H03K19/1778 , H03K21/08
Abstract: An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that has a second comparator circuit that compares the supply voltage to the threshold voltage to generate a second detection signal that indicates the decrease, and a second timestamp storage circuit that stores a second timestamp in response to the second detection signal indicating the decrease. The integrated circuit includes a control circuit that determines a location of a source of the decrease in the integrated circuit based on the first and the second timestamps.
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公开(公告)号:US20210036705A1
公开(公告)日:2021-02-04
申请号:US17074245
申请日:2020-10-19
Applicant: Intel Corporation
Inventor: Karthik Chandrasekar , Guang Chen , Wendemagegnehu T. Beyene , Ravi Prakash Gutala
IPC: H03K19/17772 , H01L25/18 , H01L23/538 , H01L23/00 , G06F30/34
Abstract: A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.
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公开(公告)号:US10243561B2
公开(公告)日:2019-03-26
申请号:US15852814
申请日:2017-12-22
Applicant: Intel Corporation
Inventor: Archanna Srinivasan , Guang Chen , Jun Pin Tan
IPC: H03K19/003 , H03K19/00 , H03K19/177 , G11C7/00
Abstract: An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.
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公开(公告)号:US20190131976A1
公开(公告)日:2019-05-02
申请号:US16234231
申请日:2018-12-27
Applicant: Intel Corporation
Inventor: Karthik Chandrasekar , Guang Chen , Wendemagegnehu T. Beyene , Ravi Prakash Gutala
IPC: H03K19/177 , H01L25/18 , H01L23/538 , H01L23/00 , G06F17/50
Abstract: A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.
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6.
公开(公告)号:US12249988B2
公开(公告)日:2025-03-11
申请号:US17353549
申请日:2021-06-21
Applicant: Intel Corporation
Inventor: Ping-Chen Liu , Guang Chen , Venu Kondapalli
IPC: H03K21/40 , G06F1/28 , H03K19/1778 , H03K21/08
Abstract: An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that has a second comparator circuit that compares the supply voltage to the threshold voltage to generate a second detection signal that indicates the decrease, and a second timestamp storage circuit that stores a second timestamp in response to the second detection signal indicating the decrease. The integrated circuit includes a control circuit that determines a location of a source of the decrease in the integrated circuit based on the first and the second timestamps.
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公开(公告)号:US20240332222A1
公开(公告)日:2024-10-03
申请号:US18129443
申请日:2023-03-31
Applicant: Intel Corporation
Inventor: Archanna Srinivasan , Guang Chen
IPC: H01L23/64 , H01L23/498 , H01L25/16
CPC classification number: H01L23/642 , H01L23/49816 , H01L25/16
Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes plurality of metal-insulator-metal capacitor units and a control circuit to dynamically select different amounts of the plurality of metal-insulator-metal capacitor units in correlation to a type of operation in a semiconductor die.
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公开(公告)号:US11444624B2
公开(公告)日:2022-09-13
申请号:US17074245
申请日:2020-10-19
Applicant: Intel Corporation
Inventor: Karthik Chandrasekar , Guang Chen , Wendemagegnehu T. Beyene , Ravi Prakash Gutala
IPC: H03K19/17772 , H01L25/18 , H01L23/538 , H01L23/00 , G06F30/34 , H02M3/04 , H02M3/156
Abstract: A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.
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公开(公告)号:US12292752B2
公开(公告)日:2025-05-06
申请号:US17031446
申请日:2020-09-24
Applicant: Intel Corporation
Inventor: Aurelien Mozipo , Archanna Srinivasan , Guang Chen , Janani Chandrasekhar
IPC: G05F1/56 , H03K17/22 , H03K19/17736
Abstract: An electronic system includes first, second, third, and fourth integrated circuit dies. The third integrated circuit die has a first voltage regulator circuit. A supply voltage output of the first voltage regulator circuit is coupled to provide a first supply voltage to a supply voltage input of the first integrated circuit die. The first voltage regulator circuit generates a first power ready signal that indicates when the first supply voltage has reached a first threshold voltage. The fourth integrated circuit die has a second voltage regulator circuit that generates a second supply voltage in response to the first power ready signal. A supply voltage output of the second voltage regulator circuit is coupled to provide the second supply voltage to a supply voltage input of the second integrated circuit die.
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公开(公告)号:US10812085B2
公开(公告)日:2020-10-20
申请号:US16234231
申请日:2018-12-27
Applicant: Intel Corporation
Inventor: Karthik Chandrasekar , Guang Chen , Wendemagegnehu T. Beyene , Ravi Prakash Gutala
IPC: H03K19/17772 , H01L25/18 , H01L23/538 , H01L23/00 , G06F30/34 , H02M3/04 , H02M3/156
Abstract: A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.
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