公开(公告)号：US12086460B2

公开(公告)日：2024-09-10

申请号：US17132672

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Jun Pin Tan ,  Yi Peng

IPC: G06F3/06 ,  G06F1/06 ,  G06F30/343

CPC classification number: G06F3/0659 ,  G06F1/06 ,  G06F3/0616 ,  G06F3/0673 ,  G06F30/343

Abstract: Systems and methods for non-destructive readback and writeback of an integrated circuit system are provided. Such a system may include an adaptive logic element including a first register pair. The first register pair may include a first register operating at a first frequency and a second register operating at a second frequency. The second frequency may be equal to or lower than the first frequency. The second register may store data from the first register. The adaptive logic element may also include a first clock providing a first clock signal to the first register and a second clock providing a second clock signal. The adaptive logic element may also include a multiplexer that may select the first clock signal or the second clock signal as a clock source for the second register.

公开(公告)号：US11334263B2

公开(公告)日：2022-05-17

申请号：US15868627

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  David Greenhill ,  Sean R. Atsatt ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/0873 ,  H03K19/17736 ,  G11C7/22 ,  G11C5/02 ,  G06F12/0875 ,  G06F30/34 ,  G11C5/04 ,  G11C7/10

Abstract: An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.

公开(公告)号：US10528413B2

公开(公告)日：2020-01-07

申请号：US15477859

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Jun Pin Tan ,  Kiun Kiet Jong

IPC: G06F11/00 ,  G06F11/07 ,  G06F17/50

Abstract: A prioritized error detection schedule may be generated using computer-aided-design (CAD) tools that receive specifications of critical regions within an array of configuration random access memory (CRAM) cells on an integrated circuit. Each of the specified critical regions may be provided a respective criticality weight. The proportion of indices in a prioritized error detection schedule that prescribe error detection for a given critical region may be based on the criticality weight of the given critical region. A prioritized error detection schedule may prescribe more frequent error correction for critical regions with higher criticality weights relative to critical regions with lower criticality weights. Addressing circuitry on the integrated circuit may be used to read out data from critical regions of CRAM in the order prescribed by the prioritized error detection schedule and check the read out CRAM data for errors.

公开(公告)号：US10243561B2

公开(公告)日：2019-03-26

申请号：US15852814

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Guang Chen ,  Jun Pin Tan

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/177 ,  G11C7/00

Abstract: An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.

公开(公告)号：US20180285190A1

公开(公告)日：2018-10-04

申请号：US15477859

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Jun Pin Tan ,  Kiun Kiet Jong

IPC: G06F11/07 ,  G06F17/50

Abstract: A prioritized error detection schedule may be generated using computer-aided-design (CAD) tools that receive specifications of critical regions within an array of configuration random access memory (CRAM) cells on an integrated circuit. Each of the specified critical regions may be provided a respective criticality weight. The proportion of indices in a prioritized error detection schedule that prescribe error detection for a given critical region may be based on the criticality weight of the given critical region. A prioritized error detection schedule may prescribe more frequent error correction for critical regions with higher criticality weights relative to critical regions with lower criticality weights. Addressing circuitry on the integrated circuit may be used to read out data from critical regions of CRAM in the order prescribed by the prioritized error detection schedule and check the read out CRAM data for errors.

公开(公告)号：US11487445B2

公开(公告)日：2022-11-01

申请号：US15358738

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Aravind Dasu ,  Scott Weber ,  Jun Pin Tan ,  Arifur Rahman

IPC: G06F9/46 ,  G06F3/06 ,  G06F15/78 ,  G11C5/02 ,  G11C5/06

Abstract: A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.

公开(公告)号：US11257526B2

公开(公告)日：2022-02-22

申请号：US15868304

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  Sean R. Atsatt ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: G11C5/02 ,  H03K19/1776 ,  G11C5/04 ,  G11C5/06

Abstract: An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.

公开(公告)号：US11086788B2

公开(公告)日：2021-08-10

申请号：US15599122

申请日：2017-05-18

Applicant: Intel Corporation

Inventor： Jun Pin Tan

IPC: G06F12/1009 ,  G11C29/00 ,  G11C29/04 ,  G06F30/33 ,  G06F30/331 ,  G11C29/08 ,  G11C29/48

Abstract: Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit as a device under test (DUT). During hardware emulation operations, an emulation host may be used to coordinate testing of the DUT on the programmable device. In particular, the programmable device may include configurable memory elements such as lookup-table random-access memory (LUTRAM) elements that are operable in a LUT mode and a memory mode. An emulation controller may be used to dynamically assert a global emulation request signal, which forces each LUTRAM element that belong to the DUT in the LUT mode, thereby allowing the emulation host to readily access their internal states without having to perform partial reconfiguration.

公开(公告)号：US20180336935A1

公开(公告)日：2018-11-22

申请号：US15599122

申请日：2017-05-18

Applicant: Intel Corporation

Inventor： Jun Pin Tan

IPC: G11C7/10 ,  G06F9/455 ,  G06F12/1009

Abstract: Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit as a device under test (DUT). During hardware emulation operations, an emulation host may be used to coordinate testing of the DUT on the programmable device. In particular, the programmable device may include configurable memory elements such as lookup-table random-access memory (LUTRAM) elements that are operable in a LUT mode and a memory mode. An emulation controller may be used to dynamically assert a global emulation request signal, which forces each LUTRAM element that belong to the DUT in the LUT mode, thereby allowing the emulation host to readily access their internal states without having to perform partial reconfiguration.

公开(公告)号：US20190044514A1

公开(公告)日：2019-02-07

申请号：US15852814

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Guang Chen ,  Jun Pin Tan

IPC: H03K19/003 ,  H03K19/177 ,  H03K19/00

Abstract: An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.