公开(公告)号：US20220172857A1

公开(公告)日：2022-06-02

申请号：US17107717

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Seyedhamed M BARGHI ,  Shyam Benegal KADALI ,  Marvin Y. PAIK ,  Sheng-Po FANG ,  Leonard P. GULER ,  Charles H. WALLACE ,  James Y. JEONG

IPC: G21K1/06 ,  G03F1/22 ,  G03F1/78 ,  G03F7/20

Abstract: Embodiments disclosed herein include methods of patterning a back end of line (BEOL) stack and the resulting structures. In an embodiment a method of patterning a BEOL stack comprises forming a grating over an interlayer dielectric (ILD), and forming a spacer over the grating. In an embodiment, the spacer is etch selective to the grating. In an embodiment, the method further comprises disposing a hardmask over the grating and the spacer, and patterning the hardmask to form an opening in the hardmask. In an embodiment, the method further comprises filling the opening with a plug, removing the hardmask, and etching the spacer. In an embodiment, a portion of the spacer is protected from the etch by the plug. In an embodiment, the method may further comprise removing the plug, and transferring the grating into the ILD with an etching process.

公开(公告)号：US20230101107A1

公开(公告)日：2023-03-30

申请号：US17485299

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： AKM Shaestagir CHOWDHURY ,  Debashish BASU ,  Githin F. ALAPATT ,  Justin E. MUELLER ,  James Y. JEONG

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: An integrated circuit structure comprises a first metal layer having first conductive features. A second metal layer has second conductive features. A via layer is in an insulating layer between the first metal layer and the second metal layer. First vias and second vias are formed in the insulating layer. The first vias have a first aspect ratio greater than a second aspect ratio of the second vias. A barrier-less metal partially fills the first vias and fills the second vias. A pure metal fills a remainder of the first vias.