公开(公告)号：US20220102554A1

公开(公告)日：2022-03-31

申请号：US17033453

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jeremy J. GUTTMAN ,  Shyam Benegal KADALI ,  Szuya S. LIAO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: Gate and fin trim isolation for advanced integrated circuit structure fabrication is described. For example, a method of fabricating an integrated circuit structure includes forming a plurality of fins along a first direction, removing a portion of one of the plurality of fins to form a trench, forming an isolation structure in the trench, the isolation structure extending above the one of the plurality of fins, forming a gate structure over the plurality of fins, the gate structure along a second direction orthogonal to the first direction, forming a dielectric spacer along sidewalls of the gate structure and the isolation structure, and, subsequent to forming the dielectric spacer, forming epitaxial source or drain structures in or on the plurality of fins.

公开(公告)号：US20240178227A1

公开(公告)日：2024-05-30

申请号：US18072564

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Venkata Aditya ADDEPALLI ,  Shyam Benegal KADALI

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/82385 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: Integrated circuit structures having uniformity among varying gate trench widths are described. For example, an integrated circuit structure includes a first fin, and a first gate trench over the first fin, the first gate trench having a first width. The integrated circuit structure also includes a second fin, and a second gate trench over the second fin, the second gate trench having a second width greater than the first width. The integrated circuit structure also includes a gate electrode layer having a first portion along a bottom and partially along sidewalls of the first trench, and the gate electrode layer having a second portion along a bottom and partially along sidewalls of the second trench, wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench.

公开(公告)号：US20220172857A1

公开(公告)日：2022-06-02

申请号：US17107717

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Seyedhamed M BARGHI ,  Shyam Benegal KADALI ,  Marvin Y. PAIK ,  Sheng-Po FANG ,  Leonard P. GULER ,  Charles H. WALLACE ,  James Y. JEONG

IPC: G21K1/06 ,  G03F1/22 ,  G03F1/78 ,  G03F7/20

Abstract: Embodiments disclosed herein include methods of patterning a back end of line (BEOL) stack and the resulting structures. In an embodiment a method of patterning a BEOL stack comprises forming a grating over an interlayer dielectric (ILD), and forming a spacer over the grating. In an embodiment, the spacer is etch selective to the grating. In an embodiment, the method further comprises disposing a hardmask over the grating and the spacer, and patterning the hardmask to form an opening in the hardmask. In an embodiment, the method further comprises filling the opening with a plug, removing the hardmask, and etching the spacer. In an embodiment, a portion of the spacer is protected from the etch by the plug. In an embodiment, the method may further comprise removing the plug, and transferring the grating into the ILD with an etching process.