公开(公告)号：US11023247B2

公开(公告)日：2021-06-01

申请号：US16024151

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Daniel Willis ,  Jonathan Thibado ,  Eugene Nelson

IPC: G06F9/38 ,  G06F9/30 ,  H01L23/31

Abstract: The systems and methods disclosed herein provide an improved processor package to determine a connection type between the package and an external circuit and to optimize processor performance based on the connection type. As a non-limiting example, a processor package consistent with the present disclosure may include a central processing unit (CPU) die and a plurality of pins (including two connection detection pins) to connect the package to a motherboard. The CPU die may include connection determination logic and execution policy logic, implemented via processor code (“p-code”), as well as a more typical processor.

公开(公告)号：US20190042270A1

公开(公告)日：2019-02-07

申请号：US16024151

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Daniel Willis ,  Jonathan Thibado ,  Eugene Nelson

IPC: G06F9/38 ,  G06F9/30

Abstract: The systems and methods disclosed herein provide an improved processor package to determine a connection type between the package and an external circuit and to optimize processor performance based on the connection type. As a non-limiting example, a processor package consistent with the present disclosure may include a central processing unit (CPU) die and a plurality of pins (including two connection detection pins) to connect the package to a motherboard. The CPU die may include connection determination logic and execution policy logic, implemented via processor code (“p-code”), as well as a more typical processor.

公开(公告)号：US20170178994A1

公开(公告)日：2017-06-22

申请号：US14975943

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Michael Hui ,  Rashelle Yee ,  Jonathan Thibado ,  Daniel P. Carter ,  Shelby Ferguson ,  Anthony P. Valpiani ,  Russell S. Aoki ,  Jonathon Robert Carstens ,  Joseph J. Jasniewski ,  Harvey R. Kofstad ,  Michael Brazel ,  Tracy Clack ,  Viktor Vogman ,  Penny Woodcock ,  Kevin J. Ceurter ,  Hongfei Yan

IPC: H01L23/34 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/345 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2224/81908 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: Disclosed herein are integrated circuit (IC) package support structures, and related systems, devices, and methods. In some embodiments, an IC package support structure may include a first heater trace, and a second heater trace, wherein the second heater trace is not conductively coupled to the first heater trace in the IC package support structure.