公开(公告)号：US20250006568A1

公开(公告)日：2025-01-02

申请号：US18216909

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY

IPC: H01L23/14 ,  H01L23/00 ,  H01L23/15

Abstract: Structures having alternative carriers for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure including a device layer, and a plurality of metallization layers above the device layer. A backside structure is below the device layer. A carrier wafer or substrate is bonded directly to and is in contact with the front side structure, or is bonded to the front side structure by a compliant bonding layer.

公开(公告)号：US20240332302A1

公开(公告)日：2024-10-03

申请号：US18129874

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Debaleena NANDI ,  Ehren MANNEBACH ,  Shaun MILLS

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: Integrated circuit structures having backside conductive source or drain contacts having enhanced contact area, and methods of fabricating integrated circuit structures having backside conductive source or drain contacts having enhanced contact area, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires or a fin. An epitaxial source or drain structure is laterally adjacent to and coupled to the vertical stack of horizontal nanowires or the fin. The epitaxial source or drain structure has a recess within a laterally surrounding outer portion. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is over and in contact with the epitaxial source or drain structure. The conductive source or drain contact is within the recess in the epitaxial source or drain structure.

公开(公告)号：US20240421153A1

公开(公告)日：2024-12-19

申请号：US18209971

申请日：2023-06-14

Applicant: Intel Corporation

Inventor： Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Ehren MANNEBACH ,  Shaun MILLS

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: Integrated circuit structures having backside contact reveal uniformity, and methods of fabricating integrated circuit structures having backside contact reveal uniformity, are described. In an example, an integrated circuit structure includes an integrated circuit structure including a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive source or drain contact is vertically beneath and in contact with a bottom of the epitaxial source or drain structure. The conductive source or drain contact is in a cavity in the isolation layer. The isolation layer extends laterally beneath the gate stack.

公开(公告)号：US20240313096A1

公开(公告)日：2024-09-19

申请号：US18121701

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/41766 ,  H01L29/42392

Abstract: Integrated circuit structures having back-side contact selectivity are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A hardmask material is below a bottom of the epitaxial source or drain structure. A conductive gate contact is vertically beneath and in contact with a bottom of the gate stack, the conductive gate contact extending under and in contact with a portion of the hardmask material.

公开(公告)号：US20250107183A1

公开(公告)日：2025-03-27

申请号：US18372514

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Gilbert DEWEY ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Ehren MANNEBACH ,  Shaun MILLS ,  Charles H. WALLACE

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having differentiated source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width and a composition. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having the composition of the first epitaxial source or drain structure, and the second epitaxial source or drain structure having a lateral width less than the lateral width of the first epitaxial source or drain structure.

公开(公告)号：US20240429291A1

公开(公告)日：2024-12-26

申请号：US18214262

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Shaun MILLS ,  Ehren MANNEBACH

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having backside source or drain contact selectivity are described. In an example, an integrated circuit structure includes a first epitaxial source or drain structure at an end of a first plurality of horizontally stacked nanowires or fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at an end of a second plurality of horizontally stacked nanowires or fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact.

公开(公告)号：US20240421101A1

公开(公告)日：2024-12-19

申请号：US18211084

申请日：2023-06-16

Applicant: Intel Corporation

Inventor： Sunny CHUGH ,  Rahim KASIM ,  Mohammad Enamul KABIR ,  Jasmeet S. CHAWLA ,  Mauro J. KOBRINSKY ,  Joseph D’SILVA

IPC: H01L23/00 ,  H01L23/50 ,  H01L23/58

Abstract: Guard rings are described. In an example, a semiconductor die includes an active device layer including a plurality of nanoribbon devices. A dielectric structure is over the active device layer. A first die-edge metal guard ring is in the dielectric structure and around an outer perimeter of the plurality of nanoribbon devices. A plurality of metallization layers is in the dielectric structure and within the first die-edge metal guard ring. A plurality of direct backside contacts extend to the active device layer. A plurality of backside metallization structures is beneath the plurality of direct backside contacts. The plurality of direct backside contacts are connected to the plurality of backside metallization structures. A second die-edge metal guard ring is laterally around the plurality of backside metallization structures.

公开(公告)号：US20240405085A1

公开(公告)日：2024-12-05

申请号：US18204204

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Patrick MORROW

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

Abstract: Integrated circuit structures having backside contact stitching are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires. First and second epitaxial source or drain structure are at respective ends of the first and second pluralities of horizontally stacked nanowires. A conductive contact structure is beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure, and the conductive contact structure is continuous between the first and second epitaxial source or drain structures. The conductive contact structure has a first vertical thickness beneath the first and second epitaxial source or drain structures greater than a second vertical thickness in a region between the first and second epitaxial source or drain structures.

公开(公告)号：US20240332175A1

公开(公告)日：2024-10-03

申请号：US18129400

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Joseph D’SILVA ,  Ehren MANNEBACH ,  Mauro J. KOBRINSKY

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/5283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7869 ,  H01L29/78696

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming backside contacts on a transistor structure by forming, during front-side processing, trenches through the transistor structure into a silicon wafer, and then, using a catalytic oxidant material that is subsequently removed, forming an oxide structure in the silicon wafer around the trenches to isolate the backside gate contact from the source/drain trenches. Other embodiments may be described and/or claimed.

公开(公告)号：US20240332172A1

公开(公告)日：2024-10-03

申请号：US18129872

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Makram ABD El QADER

IPC: H01L23/528 ,  H01L29/423

CPC classification number: H01L23/528 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/785

Abstract: Integrated circuit structures having backside contact widening are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive gate contact is vertically beneath and in contact with a bottom of the gate stack. The conductive gate contact is in a cavity in an isolation layer, the cavity extending beyond the gate stack in a direction parallel with the epitaxial source or drain structure, and the cavity confined to the gate stack in a direction toward the epitaxial source or drain structure.