公开(公告)号：US20220102506A1

公开(公告)日：2022-03-31

申请号：US17033373

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kevin COOK ,  Anand S. MURTHY ,  Gilbert DEWEY ,  Nazila HARATIPOUR ,  Chi-Hing CHOI ,  Jitendra Kumar JHA ,  Srijit MUKHERJEE

IPC: H01L29/40 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417

Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of making such devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first interface material over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type that is opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, and a second interface material over the second source region and the second drain region.

公开(公告)号：US20220416043A1

公开(公告)日：2022-12-29

申请号：US17359422

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Rushabh SHAH ,  Kevin COOK ,  Anupama BOWONDER

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/08 ,  H01L29/417

Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprising germanium, silicon and boron that at least partially covers the epitaxial source or drain structures to provide low contact resistivity.

公开(公告)号：US20220102510A1

公开(公告)日：2022-03-31

申请号：US17033362

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kevin COOK ,  Anand S. MURTHY ,  Gilbert DEWEY ,  Nazila HARATIPOUR ,  Ralph Thomas TROEGER ,  Christopher J. JEZEWSKI ,  I-Cheng TUNG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/45 ,  H01L27/092 ,  H01L21/8238

Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.