公开(公告)号：US20250142870A1

公开(公告)日：2025-05-01

申请号：US19004029

申请日：2024-12-27

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H10D30/62 ,  H10D30/01 ,  H10D62/822

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20230043665A1

公开(公告)日：2023-02-09

申请号：US17968558

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Stephen CEA ,  Biswajeet GUHA ,  Anupama BOWONDER ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/06 ,  H01L29/267

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

公开(公告)号：US20230343826A1

公开(公告)日：2023-10-26

申请号：US18216563

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Anupama BOWONDER ,  Aaron BUDREVICH ,  Tahir GHANI

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66636 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

公开(公告)号：US20230275157A1

公开(公告)日：2023-08-31

申请号：US18143549

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7853 ,  H01L29/66818 ,  H01L29/165 ,  H01L29/7851

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20200219975A1

公开(公告)日：2020-07-09

申请号：US16238858

申请日：2019-01-03

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Anupama BOWONDER ,  Aaron BUDREVICH ,  Tahir GHANI

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

公开(公告)号：US20250006733A1

公开(公告)日：2025-01-02

申请号：US18214898

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Swapnadip GHOSH ,  Chiao-Ti HUANG ,  Amritesh RAI ,  Akitomo MATSUBAYASHI ,  Fariha KHAN ,  Anupama BOWONDER ,  Reken PATEL ,  Chi-Hing CHOI

IPC: H01L27/092 ,  H01L21/8238

Abstract: Integrated circuit structures having differential epitaxial source or drain dent are described. For example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires or fin. A second sub-fin structure is beneath a second stack of nanowires or fin. A first epitaxial source or drain structure is at an end of the first stack of nanowires of fin, the first epitaxial source or drain structure having no dent or a shallower dent therein. A second epitaxial source or drain structure is at an end of the second stack of nanowires or fin, the second epitaxial source or drain structure having a deeper dent therein.

公开(公告)号：US20240274718A1

公开(公告)日：2024-08-15

申请号：US18643632

申请日：2024-04-23

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/165 ,  H01L29/66818 ,  H01L29/7851

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20230131126A1

公开(公告)日：2023-04-27

申请号：US18088469

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Rahul PANDEY ,  Rishabh MEHANDRU ,  Anupama BOWONDER ,  Pratik PATEL

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/08

Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20220416043A1

公开(公告)日：2022-12-29

申请号：US17359422

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Rushabh SHAH ,  Kevin COOK ,  Anupama BOWONDER

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/08 ,  H01L29/417

Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprising germanium, silicon and boron that at least partially covers the epitaxial source or drain structures to provide low contact resistivity.

公开(公告)号：US20200006491A1

公开(公告)日：2020-01-02

申请号：US16022508

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Biswajeet GUHA ,  Anupama BOWONDER ,  Tahir GHANI

IPC: H01L29/165 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/417 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a relatively high germanium content are described. In an example, an integrated circuit structure includes a fin including a semiconductor material. A gate stack is over an upper fin portion of the fin. A first epitaxial source or drain structure is embedded in the fin at a first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at a second side of the gate stack. The first and second epitaxial source or drain structures include silicon and germanium and have a same or greater atomic concentration of germanium than the fin.