公开(公告)号：US20220102506A1

公开(公告)日：2022-03-31

申请号：US17033373

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kevin COOK ,  Anand S. MURTHY ,  Gilbert DEWEY ,  Nazila HARATIPOUR ,  Chi-Hing CHOI ,  Jitendra Kumar JHA ,  Srijit MUKHERJEE

IPC: H01L29/40 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417

Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of making such devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first interface material over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type that is opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, and a second interface material over the second source region and the second drain region.

公开(公告)号：US20250006733A1

公开(公告)日：2025-01-02

申请号：US18214898

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Swapnadip GHOSH ,  Chiao-Ti HUANG ,  Amritesh RAI ,  Akitomo MATSUBAYASHI ,  Fariha KHAN ,  Anupama BOWONDER ,  Reken PATEL ,  Chi-Hing CHOI

IPC: H01L27/092 ,  H01L21/8238

Abstract: Integrated circuit structures having differential epitaxial source or drain dent are described. For example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires or fin. A second sub-fin structure is beneath a second stack of nanowires or fin. A first epitaxial source or drain structure is at an end of the first stack of nanowires of fin, the first epitaxial source or drain structure having no dent or a shallower dent therein. A second epitaxial source or drain structure is at an end of the second stack of nanowires or fin, the second epitaxial source or drain structure having a deeper dent therein.

公开(公告)号：US20220416050A1

公开(公告)日：2022-12-29

申请号：US17359327

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Cory BOMBERGER ,  Gilbert DEWEY ,  Anand S. MURTHY ,  Mauro KOBRINSKY ,  Rushabh SHAH ,  Chi-Hing CHOI ,  Harold W. KENNEL ,  Omair SAADAT ,  Adedapo A. ONI ,  Nazila HARATIPOUR ,  Tahir GHANI

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

公开(公告)号：US20230420456A1

公开(公告)日：2023-12-28

申请号：US17850782

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Imola ZIGONEANU ,  Gilbert DEWEY ,  Anant H. JAHAGIRDAR ,  Harold W. KENNEL ,  Pratik PATEL ,  Anand S. MURTHY ,  Chi-Hing CHOI ,  Mauro J. KOBRINSKY ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L27/0886 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/161 ,  H01L29/167

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm2.

公开(公告)号：US20230317789A1

公开(公告)日：2023-10-05

申请号：US17710841

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Anand S. MURTHY ,  Cory BOMBERGER ,  Subrina RAFIQUE ,  Chi-Hing CHOI ,  Mohammad HASAN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/41783

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with selective silicide contacts thereon are described. In an example, an integrated circuit structure includes a plurality of stacks of nanowires. A plurality of epitaxial source or drain structures is around ends of corresponding ones of the stacks of nanowires. A silicide layer is on an entirety of a top surface of the plurality of epitaxial source or drain structures. A conductive trench contact is on the silicide layer. A dielectric layer is vertically intervening between a portion of the conductive trench contact and the silicide layer.