公开(公告)号：US12293237B2

公开(公告)日：2025-05-06

申请号：US18545912

申请日：2023-12-19

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F9/50 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/30

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US10922143B2

公开(公告)日：2021-02-16

申请号：US16107691

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F1/00 ,  G06F9/50 ,  G06F1/329 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US20240118942A1

公开(公告)日：2024-04-11

申请号：US18545912

申请日：2023-12-19

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F9/50 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/30

CPC classification number: G06F9/5083 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/3009 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/5094 ,  Y02D10/00

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US11853809B2

公开(公告)日：2023-12-26

申请号：US17857394

申请日：2022-07-05

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F1/00 ,  G06F9/50 ,  G06F1/329 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30

CPC classification number: G06F9/5083 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/3009 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/5094 ,  Y02D10/00

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US20210263782A1

公开(公告)日：2021-08-26

申请号：US17173100

申请日：2021-02-10

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F9/50 ,  G06F1/329 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US20220334887A1

公开(公告)日：2022-10-20

申请号：US17857394

申请日：2022-07-05

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F9/50 ,  G06F1/329 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US11409577B2

公开(公告)日：2022-08-09

申请号：US17173100

申请日：2021-02-10

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F1/00 ,  G06F9/50 ,  G06F1/329 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US10037227B2

公开(公告)日：2018-07-31

申请号：US14973009

申请日：2015-12-17

Applicant: INTEL CORPORATION

Inventor： Guy Therien ,  Guy Sotomayor ,  Arijit Biswas ,  Michael D. Powell ,  Eric J. Dehaemer

IPC: G06F9/46 ,  G06F9/48 ,  G06F1/32 ,  G06F9/50 ,  G06F9/4401

CPC classification number: G06F9/4856 ,  G06F1/3287 ,  G06F9/4418 ,  G06F9/461 ,  G06F9/4893 ,  G06F9/5094 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D10/44

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

公开(公告)号：US09442559B2

公开(公告)日：2016-09-13

申请号：US13830157

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Arijit Biswas ,  Michael D. Powell

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A disclosed method includes accessing characterization data indicating first and second sets of performance characteristics for first and second processing cores of a processor; determining, based on a performance objective and the characterization data, a first power state for the first processing core and a second power state for the second processing core; and applying the first power performance objective to the first processing core and the second power performance objective to the second processing core.

Abstract translation: 所公开的方法包括访问指示处理器的第一和第二处理核心的第一和第二组性能特征的表征数据; 基于性能目标和所述表征数据确定所述第一处理核心的第一功率状态和所述第二处理核心的第二功率状态; 以及将所述第一功率性能目标应用于所述第一处理核心和所述第二功率性能目标到所述第二处理核心。

公开(公告)号：US20140281610A1

公开(公告)日：2014-09-18

申请号：US13830157

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Arijit Biswas ,  Michael D. Powell

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A disclosed method includes accessing characterization data indicating first and second sets of performance characteristics for first and second processing cores of a processor; determining, based on a performance objective and the characterization data, a first power state for the first processing core and a second power state for the second processing core; and applying the first power performance objective to the first processing core and the second power performance objective to the second processing core.

Abstract translation: 所公开的方法包括访问指示处理器的第一和第二处理核心的第一和第二组性能特征的表征数据; 基于性能目标和所述表征数据确定所述第一处理核心的第一功率状态和所述第二处理核心的第二功率状态; 以及将所述第一功率性能目标应用于所述第一处理核心和所述第二功率性能目标到所述第二处理核心。