公开(公告)号：US12093100B2

公开(公告)日：2024-09-17

申请号：US17033753

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Yee-Kwong Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Paul Haake ,  Andrew Herdrich ,  Ripan Das ,  Nazar Syed Haider ,  Aman Sewani

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

CPC classification number: G06F1/28 ,  G06F1/30 ,  G06F13/20 ,  G06F2213/40

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US20250004536A1

公开(公告)日：2025-01-02

申请号：US18216456

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Adwait Purandare ,  Ankush Varma ,  Nilanjan Palit ,  Yuval Bustan ,  Eran Barnett ,  Eliezer Weissman ,  Stanley Chen ,  Arjan Van De Ven

IPC: G06F1/3296 ,  G06F1/324

Abstract: Techniques and mechanisms for determining operation a processor core which is in a common power delivery domain with one or more other processor cores. In an embodiment, an execution of instructions by a first core of a processor module is selectively throttled based on the detection of a single violation condition. The throttling is performed while the cores of the processor module are each maintained in a current power state. The single violation condition comprises a violation of a test criteria by the first core, while the one or more other cores of the module each satisfy the test criteria. In the case of a multiple violation condition, each core of the processor module is transitioned from one power state to another power state. In another embodiment, the test criteria includes or is otherwise based on a threshold level of a dynamic capacitance for a given core.

公开(公告)号：US11301298B2

公开(公告)日：2022-04-12

申请号：US16833595

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Krishnakanth Sistla ,  Nilanjan Palit ,  Abhinav Karhu ,  Eugene Gorbatov ,  Eliezer Weissmann

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

公开(公告)号：US11886918B2

公开(公告)日：2024-01-30

申请号：US17717859

申请日：2022-04-11

Applicant: INTEL CORPORATION

Inventor： Ankush Varma ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Krishnakanth Sistla ,  Nilanjan Palit ,  Abhinav Karhu ,  Eugene Gorbatov ,  Eliezer Weissmann

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

CPC classification number: G06F9/5027 ,  G06F9/4812 ,  G06F9/4881 ,  G06F9/542 ,  G06F15/8038

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

公开(公告)号：US20220100247A1

公开(公告)日：2022-03-31

申请号：US17033753

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Haake ,  Andrew Herdrich ,  Ripan Das

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US11100023B2

公开(公告)日：2021-08-24

申请号：US15718178

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ruirui Huang ,  Nilanjan Palit ,  Robert P. Adler ,  Ioannis T. Schoinas ,  Avishay Snir ,  Boris Dolgunov

IPC: G06F13/40 ,  H04L12/741 ,  G06F15/78 ,  H04L29/06

Abstract: In one example, a semiconductor die includes a plurality of agents and a fabric coupled to at least some of the plurality of agents. The fabric may include at least one router to provide communication between two or more of the plurality of agents, the at least one router coupled to a first agent of the plurality of agents, where the first agent is to send a first message to the at least one router, the first message comprising a first header including a first source identifier, and the at least one router is to validate that the first source identifier is associated with the first agent and if so to direct the first message towards a destination agent, and otherwise to prevent the first message from being directed towards the destination agent. Other embodiments are described and claimed.