公开(公告)号：US20180088944A1

公开(公告)日：2018-03-29

申请号：US15275066

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Lavanya Subramanian ,  Sreenivas Subramoney ,  Nithiyanandan Bashyam ,  Anant Nori

IPC: G06F9/30 ,  G06F12/0862 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/3009 ,  G06F9/30047 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A multi-core processor includes a plurality of cores to execute a plurality of threads and to monitor metrics for each of the plurality of threads during an interval, the metrics including stall cycle values, prefetches of a first type, and prefetches of a second type. The multi-core processor further includes criticality-aware thread prioritization (CATP) logic to compute a stall fraction for each of the plurality of threads during the interval using the stall cycle values, identify a thread with a highest stall fraction of the plurality of threads, determine the highest stall fraction is greater than a stall threshold, prioritize demand requests of the identified thread, compute a prefetch accuracy of the identified thread during the interval using the prefetches of the first type and the prefetches of the second type, determine the prefetch accuracy is greater than a prefetch threshold, and prioritize prefetch requests of the identified thread.

公开(公告)号：US09727475B2

公开(公告)日：2017-08-08

申请号：US14497740

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ishwar Agarwal ,  Yen-Cheng Liu ,  Joseph Nuzman ,  Ashok Jagannathan ,  Bahaa Fahim ,  Nithiyanandan Bashyam

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0831

CPC classification number: G06F12/0875 ,  G06F12/0831 ,  G06F2212/452

Abstract: An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.

公开(公告)号：US09195606B2

公开(公告)日：2015-11-24

申请号：US13976248

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Ragavendra Natarajan ,  Jayesh Guar ,  Nithiyanandan Bashyam ,  Mainak Chaudhuri ,  Sreenivas Subramoney

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/14 ,  G06F12/12

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/126 ,  G06F12/128 ,  G06F13/14 ,  G06F2212/62

Abstract: A cache memory eviction method includes maintaining thread-aware cache access data per cache block in a cache memory, wherein the cache access data is indicative of a number of times a cache block is accessed by a first thread, associating a cache block with one of a plurality of bins based on cache access data values of the cache block, and selecting a cache block to evict from a plurality of cache block candidates based, at least in part, upon the bins with which the cache block candidates are associated.

Abstract translation: 高速缓存存储器驱逐方法包括：将每个高速缓存块的线程感知高速缓存访​​问数据保存在高速缓冲存储器中，其中高速缓存访​​问数据指示高速缓存块被第一线程访问的次数，将高速缓存块与 基于高速缓存块的高速缓存访​​问数据值的多个仓，并且至少部分地基于与高速缓存块候选相关联的区间，从多个高速缓存块候选中选择高速缓存块。

公开(公告)号：US20140351524A1

公开(公告)日：2014-11-27

申请号：US13976248

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Ragavendra Natarajan ,  Jayesh Guar ,  Nithiyanandan Bashyam ,  Mainak Chaudhuri ,  Sreenivas Subramoney

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/126 ,  G06F12/128 ,  G06F13/14 ,  G06F2212/62

Abstract: A cache memory eviction method includes maintaining thread-aware cache access data per cache block in a cache memory, wherein the cache access data is indicative of a number of times a cache block is accessed by a first thread, associating a cache block with one of a plurality of bins based on cache access data values of the cache block, and selecting a cache block to evict from a plurality of cache block candidates based, at least in part, upon the bins with which the cache block candidates are associated.

Abstract translation: 高速缓存存储器驱逐方法包括：将每个高速缓存块的线程感知高速缓存访​​问数据保存在高速缓冲存储器中，其中高速缓存访​​问数据指示高速缓存块被第一线程访问的次数，将高速缓存块与 基于高速缓存块的高速缓存访​​问数据值的多个仓，并且至少部分地基于与高速缓存块候选相关联的区间，从多个高速缓存块候选中选择高速缓存块。