公开(公告)号：US08649818B2

公开(公告)日：2014-02-11

申请号：US13758918

申请日：2013-02-04

Applicant: Intel Corporation

Inventor： Vincent J. Zimmer ,  Michael A. Rothman ,  Palsamy Sakthikumar ,  Mallik Bulusu ,  Robert C. Swanson

IPC: H04W88/06

CPC classification number: H04W88/06 ,  G06F9/5077

Abstract: A software-defined radio (SDR) capability may be provided in a general purpose, many core processing system by sequestering one or more partitions running on one or more cores and instantiating a communications capability by having discrete SDR functions performed by the sequestered partitions. Each SDR module embodied in a sequestered partition may be independently upgraded without modifying the hardware of the underlying processing system. By executing SDR modules in cores not accessible by application programs and/or an operating system (OS), a better Quality of Service (QoS) may be provided for wireless communications on the general purpose, multi-core processing system. An embodiment comprises isolating a core of a many core processing system as a sequestered partition, loading a software-defined radio module onto the core, and executing the software-defined module to implement wireless communications.

Abstract translation: 可以在通用目的的许多核心处理系统中通过隔离在一个或多个核上运行的一个或多个分区并通过具有由隔离分区执行的离散SDR功能来实例化通信能力来提供软件定义无线电（SDR）能力。 实施在隔离分区中的每个SDR模块可以独立升级，而无需修改底层处理系统的硬件。 通过在应用程序和/或操作系统（OS）不可访问的核心中执行SDR模块，可以为通用多核处理系统上的无线通信提供更好的服务质量（QoS）。 一个实施例包括将许多核心处理系统的核心隔离为隔离分区，将软件定义的无线电模块加载到核心上，以及执行软件定义模块以实现无线通信。

公开(公告)号：US09292463B2

公开(公告)日：2016-03-22

申请号：US13627512

申请日：2012-09-26

Applicant: Intel Corporation

Inventor： David C. Estrada ,  Vincent J. Zimmer ,  Palsamy Sakthikumar

IPC: G06F13/00 ,  G06F13/40 ,  G06F9/44

CPC classification number: G06F9/4411 ,  G06F9/4406 ,  G06F13/26 ,  G06F13/4027

Abstract: Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.

Abstract translation: 各种实施例涉及创建与硬件设备相关联的多个设备块，以指示总线和桥接器层级中的硬件设备的位置的顺序排列设备块，以及使得能够从操作系统访问多个设备块。 一种装置包括处理器电路和存储器，其存储指令，其操作在所述处理器电路上以创建包括多个设备块的设备表，每个设备块对应于所述处理器电路可访问的多个硬件设备之一，所述设备块以指示 硬件设备在总线和至少一个桥接设备层级中的相对位置; 使操作系统能够访问设备表; 并且执行在处理器电路上操作的操作系统的第二指令序列以访问设备表。 在此描述和要求保护的其它实施例。

公开(公告)号：US08965749B2

公开(公告)日：2015-02-24

申请号：US13848133

申请日：2013-03-21

Applicant: Intel Corporation

Inventor： Palsamy Sakthikumar ,  Michael A. Rothman ,  Vincent J. Zimmer ,  Robert C. Swanson ,  Mallik Bulusu

IPC: G06F9/455 ,  G06F13/10 ,  G06F21/57 ,  G06F9/48

CPC classification number: G06F13/105 ,  G06F9/4812 ,  G06F21/572 ,  G06F2221/2105

Abstract: A method, apparatus, system, and computer program product for secure server system management. A payload containing system software and/or firmware updates is distributed in an on-demand, secure I/O operation. The I/O operation is performed via a secured communication channel inaccessible by the server operating system to an emulated USB drive. The secure communication channel can be established for the I/O operation only after authenticating the recipient of the payload, and the payload can be protected from access by a potentially-infected server operating system. Furthermore, the payload can be delivered on demand rather than relying on a BIOS update schedule, and the payload can be delivered at speeds of a write operation to a USB drive.

Abstract translation: 一种用于安全服务器系统管理的方法，设备，系统和计算机程序产品。 包含系统软件和/或固件更新的有效载荷以按需安全I / O操作分发。 I / O操作通过服务器操作系统无法访问到模拟USB驱动器的安全通信通道执行。 只有在验证有效负载的收件人之后，才能为I / O操作建立安全通信通道，并且可以保护有效负载免受潜在感染的服务器操作系统的访问。 此外，有效载荷可以按需传送，而不是依赖于BIOS更新计划，并且有效载荷可以以写入操作的速度传送到USB驱动器。

公开(公告)号：US10002002B2

公开(公告)日：2018-06-19

申请号：US15076384

申请日：2016-03-21

Applicant: INTEL CORPORATION

Inventor： David C. Estrada ,  Vincent J. Zimmer ,  Palsamy Sakthikumar

IPC: G06F13/36 ,  G06F9/44 ,  G06F13/40 ,  G06F13/26

CPC classification number: G06F9/4411 ,  G06F9/4406 ,  G06F13/26 ,  G06F13/4027

Abstract: Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.

公开(公告)号：US09703697B2

公开(公告)日：2017-07-11

申请号：US13728608

申请日：2012-12-27

Applicant: Intel Corporation

Inventor： Ramamurthy Krithivas ,  Palsamy Sakthikumar

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  Y02D10/13

Abstract: Methods and apparatus related to sharing Serial Peripheral Interface (SPI) flash memory in a multi-node server SoC (System on Chip) platform environment are described. In one embodiment, multi-port non-volatile memory is shared by a plurality of System on Chip (SoC) devices. Each of the plurality of SoC devices comprises controller logic to control access to the multi-port non-volatile memory and/or to translate a host referenced address of a memory access request to a linear address space and a physical address space of the multi-port non-volatile memory. Other embodiments are also disclosed and claimed.