公开(公告)号：US20230095007A1

公开(公告)日：2023-03-30

申请号：US17485173

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Stephen M. CEA ,  Aaron D. LILAK ,  Cory WEBER ,  Patrick KEYS ,  Navid PAYDAVOSI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Integrated circuit structures having metal-containing source or drain structures, and methods of fabricating integrated circuit structures having metal-containing source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include a metal species diffused therein, the metal species further diffused partially into the vertical arrangement of horizontal nanowires.

公开(公告)号：US20220416024A1

公开(公告)日：2022-12-29

申请号：US17903914

申请日：2022-09-06

Applicant: Intel Corporation

Inventor： Glenn GLASS ,  Anand MURTHY ,  Biswajeet GUHA ,  Dax CRUM ,  Patrick KEYS ,  Tahir GHANI ,  Susmita GHOSE ,  Ted COOK, JR.

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/027 ,  H01L27/092 ,  H01L21/683 ,  H01L21/8238

Abstract: Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20220310601A1

公开(公告)日：2022-09-29

申请号：US17211745

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Cory WEBER ,  Stephen M. CEA ,  Leonard C. PIPES ,  Seahee HWANGBO ,  Rishabh MEHANDRU ,  Patrick KEYS ,  Jack YAUNG ,  Tzu-Min OU

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm3. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.