公开(公告)号：US20250045219A1

公开(公告)日：2025-02-06

申请号：US18923535

申请日：2024-10-22

Applicant: Intel Corporation

Inventor： Raghavendra RAO ,  Venkata Mahesh GUNNAM ,  Eliad Adi KLEIN ,  David HINES

IPC: G06F13/16 ,  G06F13/42

Abstract: Examples include techniques associated with causing a change to a configuration to access a storage device based on determined bandwidth capabilities for read and write transactions to the storage device and based on a determined needed bandwidth to complete monitored read and write transactions to the storage device. The configuration to be based, at least in part, on coupling to the storage device via a storage interface over a serial bus and the configuration to include a link width for the serial bus, a link speed for the serial bus, or a power state to operate the storage device.

公开(公告)号：US20220272880A1

公开(公告)日：2022-08-25

申请号：US17741294

申请日：2022-05-10

Applicant: Intel Corporation

Inventor： Shailendra Singh CHAUHAN ,  Raghavendra RAO ,  Ranjul BALAKRISHNAN ,  Nizamuddin SHAIK ,  Bijendra SINGH ,  Siva Prasad JANGILI GANGA ,  Dong-Ho HAN

IPC: H05K9/00 ,  H01R12/71 ,  H01L23/32 ,  H01L23/498 ,  H01L23/552 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18

Abstract: A system board includes a module board that connects to the system board with an interposer having compressible connectors. The module board can further be covered by a shield that has a metal alloy having an element to provide good electrical conductivity and an element to provide structural integrity and heat transfer. The module board can further include gaskets to interconnect the shield to a ground plane of the module board. the interposer board can further include an extra column of ground connections to reduce signaling noise between the interposer board and the system board.

公开(公告)号：US20210321516A1

公开(公告)日：2021-10-14

申请号：US17354540

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Raghavendra RAO ,  Ranjul BALAKRISHNAN ,  Shailendra Singh CHAUHAN ,  Sandesh Krishnamurthy GEEJAGAARU

IPC: H05K1/11 ,  H05K1/14

Abstract: A memory module has pads on the top and bottom surfaces of a module printed circuit board (PCB). The pads match the pin layout of one or more memory devices to be mounted on the memory module. The pads on one surface of the PCB electrically interconnect to the memory device(s), and the pads on the other surface electrically interconnect to pads on a system board, such as a motherboard. With the pad layout on the memory module, the pad layout of the system board can be the same for a memory-down implementation and for a removable memory module. The pad layout provides good signal-to-noise performance and can enable a memory module for low power double data rate (LPDDR) memory, double data rate (DDR) memory, and graphics double data rate (GDDR) memory.