公开(公告)号：US11106438B2

公开(公告)日：2021-08-31

申请号：US16832797

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Dounia Khaldi ,  Rakesh Krishnaiyer ,  Rajiv Deodhar ,  Daniel Woodworth ,  Joshua Cranmer ,  Kent Glossop

IPC: G06F9/44 ,  G06F8/41

Abstract: Various embodiments are generally directed to optimizing dataflow in automated transformation frameworks (e.g., compiler, runtime, etc.) for spatial architectures (e.g., Configurable Spatial Accelerator) that translate high-level user code into forms that use “streams” (e.g., Latency Insensitive Channels, line buffers) to reduce overhead, eliminate or improve the efficiency of redundant memory accesses, and improve overall throughput.

公开(公告)号：US20160259628A1

公开(公告)日：2016-09-08

申请号：US14741160

申请日：2015-06-16

Applicant: Intel Corporation

Inventor： Farhana Aleen Schuchman ,  David L. Kreitzer ,  Rakesh Krishnaiyer ,  Vyacheslav Pavlovich Zakharin ,  Sergey Preis ,  Leonardo Jose Borges ,  Philippe Thierry

IPC: G06F9/44 ,  G06F11/36

CPC classification number: G06F8/30 ,  G06F8/4441 ,  G06F8/452 ,  G06F11/3688

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector loads. An example apparatus includes a node group to associate a vector operation with a node group based on a load type of the vector operation. The example apparatus also includes a candidate identifier to identify a candidate in the node group, the candidate to include a subset of vector operations of the node group. The example apparatus also includes a code optimizer to determine replacement code based on a characteristic of the candidate, and to compare an estimated cost associated with executing the replacement code to a threshold cost relative to a cost of executing the candidate. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold cost.

Abstract translation: 公开了方法，装置，系统和制品以消除部分冗余矢量载荷。 示例性装置包括基于向量操作的负载类型将向量操作与节点组相关联的节点组。 示例性装置还包括用于标识节点组中的候选的候选标识符，候选者包括节点组的向量操作的子集。 示例性装置还包括代码优化器，用于基于候选者的特征来确定替换代码，并且将与执行替换代码相关联的估计成本与执行候选的成本相比较的阈值成本进行比较。 示例性装置还包括代码生成器，当执行替换代码的估计成本满足阈值成本时，使用替换代码生成机器代码。

公开(公告)号：US10268454B2

公开(公告)日：2019-04-23

申请号：US15714606

申请日：2017-09-25

Applicant: Intel Corporation

Inventor： Farhana Aleen Schuchman ,  David L. Kreitzer ,  Rakesh Krishnaiyer ,  Vyacheslav Pavlovich Zakharin ,  Sergey Preis ,  Leonardo Jose Borges ,  Philippe Thierry

IPC: G06F8/41 ,  G06F8/30 ,  G06F11/36

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector load operations. An example apparatus includes a node grouper to associate a vector operation with a node group, a candidate verifier to perform a dependencies test on a subset of the node group, and identify a subset of the node group as a candidate when the subset satisfies the dependencies test, and a code optimizer to determine replacement code based on a characteristic of the candidate in the node group and compare an estimated cost associated with executing the replacement code to a threshold. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold.

公开(公告)号：US20190042221A1

公开(公告)日：2019-02-07

申请号：US15972345

申请日：2018-05-07

Applicant: INTEL CORPORATION

Inventor： Rakesh Krishnaiyer ,  Konstantin Bobrovskii ,  Dmitry Budanov

IPC: G06F8/41

Abstract: Logic may transform a target code to partition data automatically and/or autonomously based on a memory constraint associated with a resource such as a target device. Logic may identify a tag in the code to identify a task, wherein the task comprises at least one loop, the loop to process data elements in one or more arrays. Logic may automatically generate instructions to determine one or more partitions for the at least one loop to partition data elements, accessed by one or more memory access instructions for the one or more arrays within the at least one loop, based on a memory constraint, the memory constraint to identify an amount of memory available for allocation to process the task. Logic may determine one or more iteration space blocks for the parallel loops, determine memory windows for each block, copy data into and out of constrained memory, and transform array accesses.

公开(公告)号：US20180011693A1

公开(公告)日：2018-01-11

申请号：US15714606

申请日：2017-09-25

Applicant: Intel Corporation

Inventor： Farhana Aleen Schuchman ,  David L. Kreitzer ,  Rakesh Krishnaiyer ,  Vyacheslav Pavlovich Zakharin ,  Sergey Preis ,  Leonardo Jose Borges ,  Philippe Thierry

IPC: G06F9/44 ,  G06F9/45 ,  G06F11/36

CPC classification number: G06F8/30 ,  G06F8/4441 ,  G06F8/452 ,  G06F11/3688

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector load operations. An example apparatus includes a node grouper to associate a vector operation with a node group, a candidate verifier to perform a dependencies test on a subset of the node group, and identify a subset of the node group as a candidate when the subset satisfies the dependencies test, and a code optimizer to determine replacement code based on a characteristic of the candidate in the node group and compare an estimated cost associated with executing the replacement code to a threshold. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold.

公开(公告)号：US20220012028A1

公开(公告)日：2022-01-13

申请号：US17483459

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Charles Yount ,  Rakesh Krishnaiyer ,  Timothy Creech ,  Daniel Woodworth ,  Joshua Cranmer

IPC: G06F8/41

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., computer readable storage media) to perform automatic compiler optimization to enable streaming-store generation for unaligned contiguous write access are disclosed. Example apparatus disclosed herein are to mark a store instruction in source program code as a transformation candidate when the store instruction is associated with a group of memory accesses that are unaligned with respect to a size of a cache line in a cache. Disclosed apparatus are also to transform the store instruction that is marked as the transformation candidate to form transformed program code when a non-temporal property is satisfied, the transformed program code to replace the store instruction with (i) a write to a buffer in the cache and (ii) a streaming-store instruction that is to write contents of the buffer to memory.

公开(公告)号：US09785413B2

公开(公告)日：2017-10-10

申请号：US14741160

申请日：2015-06-16

Applicant: Intel Corporation

Inventor： Farhana Aleen Schuchman ,  David L. Kreitzer ,  Rakesh Krishnaiyer ,  Vyacheslav Pavlovich Zakharin ,  Sergey Preis ,  Leonardo Jose Borges ,  Philippe Thierry

IPC: G06F9/45 ,  G06F9/44 ,  G06F11/36

CPC classification number: G06F8/30 ,  G06F8/4441 ,  G06F8/452 ,  G06F11/3688

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector loads. An example apparatus includes a node group to associate a vector operation with a node group based on a load type of the vector operation. The example apparatus also includes a candidate identifier to identify a candidate in the node group, the candidate to include a subset of vector operations of the node group. The example apparatus also includes a code optimizer to determine replacement code based on a characteristic of the candidate, and to compare an estimated cost associated with executing the replacement code to a threshold cost relative to a cost of executing the candidate. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold cost.

公开(公告)号：US12032934B2

公开(公告)日：2024-07-09

申请号：US17483459

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Charles Yount ,  Rakesh Krishnaiyer ,  Timothy Creech ,  Daniel Woodworth ,  Joshua Cranmer

IPC: G06F8/41

CPC classification number: G06F8/4434

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., computer readable storage media) to perform automatic compiler optimization to enable streaming-store generation for unaligned contiguous write access are disclosed. Example apparatus disclosed herein are to mark a store instruction in source program code as a transformation candidate when the store instruction is associated with a group of memory accesses that are unaligned with respect to a size of a cache line in a cache. Disclosed apparatus are also to transform the store instruction that is marked as the transformation candidate to form transformed program code when a non-temporal property is satisfied, the transformed program code to replace the store instruction with (i) a write to a buffer in the cache and (ii) a streaming-store instruction that is to write contents of the buffer to memory.

公开(公告)号：US11366647B2

公开(公告)日：2022-06-21

申请号：US16863315

申请日：2020-04-30

Applicant: Intel Corporation

Inventor： Rajiv Deodhar ,  Sergey Dmitriev ,  Daniel Woodworth ,  Rakesh Krishnaiyer ,  Kent Glossop ,  Arvind Sudarsanam

IPC: G06F9/315 ,  G06F9/38 ,  G06F9/44 ,  G06F8/41 ,  G06F9/345 ,  G06F9/32 ,  G06F9/30

Abstract: Systems, apparatuses and methods may provide for technology that detects one or more local variables in source code, wherein the local variable(s) lack dependencies across iterations of a loop in the source code, automatically generate pipeline execution code for the local variable(s), and incorporate the pipeline execution code into an output of a compiler. In one example, the pipeline execution code includes an initialization of a pool of buffer storage for the local variable(s).

公开(公告)号：US20200257510A1

公开(公告)日：2020-08-13

申请号：US16863315

申请日：2020-04-30

Applicant: Intel Corporation

Inventor： Rajiv Deodhar ,  Sergey Dmitriev ,  Daniel Woodworth ,  Rakesh Krishnaiyer ,  Kent Glossop ,  Arvind Sudarsanam

IPC: G06F8/41 ,  G06F9/38

Abstract: Systems, apparatuses and methods may provide for technology that detects one or more local variables in source code, wherein the local variable(s) lack dependencies across iterations of a loop in the source code, automatically generate pipeline execution code for the local variable(s), and incorporate the pipeline execution code into an output of a compiler. In one example, the pipeline execution code includes an initialization of a pool of buffer storage for the local variable(s).