公开(公告)号：US20210358908A1

公开(公告)日：2021-11-18

申请号：US16876495

申请日：2020-05-18

Applicant: Intel Corporation

Inventor： Robert EHLERT ,  Timothy JEN ,  Alexander BADMAEV ,  Shridhar HEGDE ,  Sandrine CHARUE-BAKKER

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/417

Abstract: Integrated circuit structures having high phosphorous dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon and phosphorous, the phosphorous having an atomic concentration in a core region of the silicon greater than an atomic concentration in a peripheral region of the silicon.

公开(公告)号：US20210399119A1

公开(公告)日：2021-12-23

申请号：US16910008

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Suresh VISHWANATH ,  Roza KOTLYAR ,  Han Wui THEN ,  Robert EHLERT ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Sandrine CHARUE-BAKKER

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L21/285 ,  H01L29/66

Abstract: Embodiments disclosed herein comprise a high electron mobility transistor (HEMT). In an embodiment, the HEMT comprises a heterojunction channel that includes a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. In an embodiment a first interface layer is between the first semiconductor layer and the second semiconductor layer, and a second interface layer is over the first interface layer. In an embodiment, the HEMT further comprises a source contact, a drain contact, and a gate contact between the source contact and the drain contact.

公开(公告)号：US20220093790A1

公开(公告)日：2022-03-24

申请号：US17030221

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Robert EHLERT ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Sandrine CHARUE-BAKKER

IPC: H01L29/78 ,  H01L29/20 ,  H01L27/092 ,  H01L29/205 ,  H01L29/40

Abstract: Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.

公开(公告)号：US20240063274A1

公开(公告)日：2024-02-22

申请号：US17889986

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Patrick WALLACE ,  Robert EHLERT ,  Subrina RAFIQUE ,  Peter WELLS ,  Anand S. MURTHY ,  Shishir PANDYA ,  Xiaochen REN ,  Yulia TOLSTOVA

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L29/41733 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/24

Abstract: In an example, an integrated circuit structure includes a first vertical stack of horizontal nanowires laterally spaced apart from a second vertical stack of horizontal nanowires. An epitaxial source or drain structure is between the first and second vertical stacks of horizontal nanowires. The epitaxial source or drain structure includes a nucleation layer having a first portion in contact with the first vertical stack of horizontal nanowires and a second portion in contact with the second vertical stack of horizontal nanowires. The nucleation layer includes silicon with arsenic dopants. The epitaxial source or drain structure also includes an epitaxial fill layer laterally between the first and second portions of the nucleation layer. The epitaxial fill layer includes silicon with phosphorous dopants. The epitaxial fill layer has a total atomic concentration of arsenic less than half of a total atomic concentration of arsenic of the nucleation layer.