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公开(公告)号：US20220337421A1
公开(公告)日：2022-10-20
申请号：US17854911
申请日：2022-06-30
Applicant: Intel Corporation
Inventor： SANTOSH GHOSH , VIKRAM SURESH , SANU MATHEW , MANOJ SASTRY , ANDREW H. REINDERS , RAGHAVAN KUMAR , RAFAEL MISOCZKI
Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.
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公开(公告)号：US20220086010A1
公开(公告)日：2022-03-17
申请号：US17534158
申请日：2021-11-23
Applicant: Intel Corporation
Inventor： VIKRAM SURESH , SANU MATHEW , MANOJ SASTRY , SANTOSH GHOSH , RAGHAVAN KUMAR , RAFAEL MISOCZKI
Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.
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3.发明公开公开(公告)号：US20240031140A1
公开(公告)日：2024-01-25
申请号：US17814448
申请日：2022-07-22
Applicant: Intel Corporation
Inventor： ANDREA BASSO , DUMITRU-DANIEL DINU , SANTOSH GHOSH , MANOJ SASTRY
CPC classification number: H04L9/0858 , H04L9/3093 , H04L9/0869
Abstract: In one example an apparatus comprises a first input node to receive a first input, a second input node to receive a control signal, a polynomial multiplication circuitry to perform a polynomial multiplication operation using the first input in a security mode determined by the control signal, the security mode comprising one of a first mode in which no side-channel protection is provided to the polynomial multiplication operation, a second mode in which a shuffling-based side-channel protection is provided to the polynomial multiplication operation, a third mode in which a masking or splitting side-channel protection is provided to the polynomial multiplication operation, or a fourth mode in which a masking and shuffling based side-channel protection is provided to the polynomial multiplication operation. Other examples may be described.
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公开(公告)号：US20210119777A1
公开(公告)日：2021-04-22
申请号：US17133183
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： SANTOSH GHOSH , Marcio Juliato , Manoj Sastry
Abstract: An apparatus comprises an input register comprising a state register and a parity field, a first round secure hash algorithm (SHA) datapath communicatively coupled to the state register, comprising a first section to perform a θ step of a SHA calculation, a second section to perform a ρ step and a ρ step of the SHA calculation, a third section to perform a χ step of the SHA calculation and a fourth section to perform a τ step of the SHA calculation.
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5.发明申请公开(公告)号：US20190319800A1
公开(公告)日：2019-10-17
申请号：US16455967
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： RAFAEL MISOCZKI , VIKRAM SURESH , DAVID WHEELER , SANTOSH GHOSH , MANOJJ SASTRY
Abstract: In one example an apparatus comprises accelerator logic to pre-compute at least a portion of a message representative, hash logic to generate the message representative based on an input message, and signature logic to generate a signature to be transmitted in association with the message representative, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and determine whether the message representative satisfies a target threshold allocation of computational costs between a cost to generate the signature and a cost to verify the signature. Other examples may be described.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190319804A1
公开(公告)日：2019-10-17
申请号：US16456187
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： SANU MATHEW , MANOJ SASTRY , SANTOSH GHOSH , VIKRAM SURESH , ANDREW H. REINDERS , RAGHAVAN KUMAR , RAFAEL MISOCZKI
Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments, according to one embodiment. A method of embodiments, as described herein, includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.
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公开(公告)号：US20190319803A1
公开(公告)日：2019-10-17
申请号：US16456064
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： RAFAEL MISOCZKI , VIKRAM SURESH , SANTOSH GHOSH , MANOJ SASTRY , SANU MATHEW , RAGHAVAN KUMAR
Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.
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公开(公告)号：US20190319796A1
公开(公告)日：2019-10-17
申请号：US16456034
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： SANTOSH GHOSH , Vikram Suresh , Sanu Mathew , Manoj Sastry , Andrew H. Reinders , Raghavan Kumar , Rafael Misoczki
Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.
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公开(公告)号：US20180088927A1
公开(公告)日：2018-03-29
申请号：US15278658
申请日：2016-09-28
Applicant: Intel Corporation
Inventor： LI ZHAO , RAFAEL MISOCZKI , SANTOSH GHOSH , MANOJ R. SASTRY
CPC classification number: H04L9/0643 , G06F21/575 , H04L9/0836 , H04L9/3236 , H04L9/3247 , H04L63/123 , H04L2209/38
Abstract: One embodiment provides an apparatus. The apparatus includes an Internet of Things (IoT) device including a processor, a memory, a flash memory, a network interface and a boot Read Only Memory (ROM). A Root-of-Trust (RoT) application stored in the boot ROM causes the processor run the RoT after initialization of the IoT device. The RoT causes the device to determine a selected image by determining if an update mode is set. The RoT also causes the processor to load the selected image into memory and determine whether a verification of a signature of the selected image is successful. When the verification of the signature is successful then control is transferred to the selected image and when the verification is not successful then a recovery boot is performed
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10.发明申请公开(公告)号：US20230017447A1
公开(公告)日：2023-01-19
申请号：US17934682
申请日：2022-09-23
Applicant: Intel Corporation
Inventor： SANU MATHEW , MANOJ SASTRY , SANTOSH GHOSH , VIKRAM SURESH , ANDREW H. REINDERS , RAGHAVAN KUMAR , RAFAEL MISOCZKI
Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments, according to one embodiment. A method of embodiments, as described herein, includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.
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