公开(公告)号：US20160110298A1

公开(公告)日：2016-04-21

申请号：US14519648

申请日：2014-10-21

Applicant: Intel Corporation

Inventor： DAVID A. KOUFATY ,  GILBERT NEIGER ,  RAJESH M. SANKARAN ,  ANDREW V. ANDERSON ,  SUBRAMANYA R. DULLOOR ,  WERNER HAAS ,  JOSEPH NUZMAN

IPC: G06F12/14 ,  G06F21/62

CPC classification number: G06F12/1466 ,  G06F21/52 ,  G06F2212/1052

Abstract: A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.

Abstract translation: 处理系统包括执行任务的处理核心和耦合到核心的存储器管理单元。 存储器管理单元包括：存储单元，用于存储包括存储器帧的一个或多个标识符的页表项，保护密钥和指示一个或多个存储器帧是否可根据用户模式访问的访问模式位，或者根据 管理员模式，包括多个字段的第一允许寄存器，每个字段包括反映用户模式下的一组存储器访问许可的位数，以及存储多个字段的第二许可寄存器，每个字段包括一组 在管理员模式下反映一组内存访问权限的位。

公开(公告)号：US20160239431A1

公开(公告)日：2016-08-18

申请号：US14621654

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： SHENG LI ,  SANJAY KUMAR ,  VICTOR W. LEE ,  RAJESH M. SANKARAN ,  SUBRAMANYA R. DULLOOR

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1045 ,  G06F9/467 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/69

Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent cache, wherein the transaction is to create a mapping from a virtual address space to a memory region identified by a memory region identifier (MRID) in the persistent memory, and tag a cache line of the non-persistent cache with the MRID, in which the cache line is associated with a cache line status, and a cache controller, in response to detecting a failure event, to selectively evict contents of the cache line to the memory region identified by the MRID based on the cache line status.

Abstract translation: 处理器包括处理核心，用于执行包括经由非永久性高速缓冲存储器与永久存储器编码事务的指令的应用程序，其中事务是创建从虚拟地址空间到由存储器区域标识符（ MRID），并且使用其中高速缓存行与高速缓存行状态相关联的MRID和高速缓存控制器将非持续高速缓存的高速缓存行标记为响应于检测到故障事件而选择性地 基于高速缓存行状态将高速缓存行的内容推送到由MRID标识的存储器区域。