公开(公告)号：US20240127392A1

公开(公告)日：2024-04-18

申请号：US17967768

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Saurabh GAYEN ,  Utkarsh Y. KAKAIYA ,  Alexander F. HEINECKE

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20

Abstract: A chip or other apparatus of an aspect includes a first accelerator and a second accelerator. The first accelerator has support for a chained accelerator operation. The first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, generate first intermediate data, and store the first intermediate data to a storage. The second accelerator also has support for the chained accelerator operation. The second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data from the storage, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.

公开(公告)号：US20240126613A1

公开(公告)日：2024-04-18

申请号：US17967740

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Saurabh GAYEN ,  Christopher J. HUGHES ,  Utkarsh Y. KAKAIYA ,  Alexander F. HEINECKE

IPC: G06F9/50 ,  G06F9/355 ,  G06F9/38

CPC classification number: G06F9/505 ,  G06F9/3555 ,  G06F9/3877

Abstract: A chip or other apparatus of an aspect includes a first accelerator and a second accelerator. The first accelerator has support for a chained accelerator operation. The first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, and generate first intermediate data. The second accelerator also has support for the chained accelerator operation. The second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.

公开(公告)号：US20230042934A1

公开(公告)日：2023-02-09

申请号：US17560170

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Sanjay KUMAR ,  Rajesh SANKARAN ,  Narayan RANGANATHAN ,  Saurabh GAYEN ,  Dhananjay JOSHI ,  Nikhil P. RAO

IPC: G06F11/07

Abstract: Apparatus and method for high-performance page fault handling. For example, one embodiment of an apparatus comprises: one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling modes including a first page fault handling mode and a second page fault handling mode.

公开(公告)号：US20220261178A1

公开(公告)日：2022-08-18

申请号：US17688710

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Yadong LI ,  Anjali Singhai JAIN ,  Kun TIAN ,  Yan ZHAO ,  Yaozu DONG ,  Baolu LU ,  Rajesh M. SANKARAN ,  Eliel LOUZOUN ,  Rupin H. VAKHARWALA ,  David HARRIMAN ,  Saurabh GAYEN ,  Philip LANTZ ,  Israel BEN SHAHAR ,  Kenneth G. KEELS

IPC: G06F3/06 ,  G06F12/10

Abstract: Examples described herein relate to a packet processing device that includes circuitry to receive an address translation for a virtual to physical address prior to receipt of a GPUDirect remote direct memory access (RDMA) operation, wherein the address translation is provided at initiation of a process executed by a host system and circuitry to apply the address translation for a received GPUDirect RDMA operation.

公开(公告)号：US20240126555A1

公开(公告)日：2024-04-18

申请号：US17967756

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Saurabh GAYEN ,  Christopher J. HUGHES ,  Utkarsh Y. KAKAIYA ,  Alexander F. HEINECKE

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/355

CPC classification number: G06F9/3836 ,  G06F9/3004 ,  G06F9/3555

Abstract: A method of an aspect includes receiving a request for a chained accelerator operation, and configuring a chain of accelerators to perform the chained accelerator operation. This may include configuring a first accelerator to access an input data from a source memory location in system memory, process the input data, and generate first intermediate data. This may also include configuring a second accelerator to receive the first intermediate data, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.

公开(公告)号：US20230040226A1

公开(公告)日：2023-02-09

申请号：US17559612

申请日：2021-12-22

Applicant: INTEL CORPORATION

Inventor： Saurabh GAYEN ,  Dhananjay JOSHI ,  Philip LANTZ ,  Rajesh SANKARAN ,  Narayan RANGANATHAN

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/30

Abstract: Apparatus and method for managing pipeline depth of a data processing device. For example, one embodiment of an apparatus comprises: an interface to receive a plurality of work requests from a plurality of clients; and a plurality of engines to perform the plurality of work requests; wherein the work requests are to be dispatched to the plurality of engines from a plurality of work queues, the work queues to store a work descriptor per work request, each work descriptor to include information needed to perform a corresponding work request, wherein the plurality of work queues include a first work queue to store work descriptors associated with first latency characteristics and a second work queue to store work descriptors associated with second latency characteristics; engine configuration circuitry to configure a first engine to have a first pipeline depth based on the first latency characteristics and to configure a second engine to have a second pipeline depth based on the second latency characteristics.

公开(公告)号：US20220350499A1

公开(公告)日：2022-11-03

申请号：US17745453

申请日：2022-05-16

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Yadong LI ,  Anjali Singhai JAIN ,  Kenneth G. KEELS ,  Andrzej SAWULA ,  Kun TIAN ,  Ashok RAJ ,  Rupin H. VAKHARWALA ,  Rajesh M. SANKARAN ,  Saurabh GAYEN ,  Baolu LU ,  Yan ZHAO

IPC: G06F3/06 ,  G06F9/455

Abstract: As described herein, for a selected process identifier and virtual address, a page fault arising from multiple sources can be solved by a one-time operation. The selected process identifier can include a virtual function (VF) identifier or process address space identifier (PASID). In some examples, solving a page fault arising from multiple sources by a one-time operation comprises invoking a page fault handler to determine an address translation.