公开(公告)号：US10942672B2

公开(公告)日：2021-03-09

申请号：US16422827

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Shrinivas Venkatraman ,  Eng Hun Ooi ,  Sahar Khalili ,  Dimpesh Patel ,  Kuan Hua Tan

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42

Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.

公开(公告)号：US20220197519A1

公开(公告)日：2022-06-23

申请号：US17128072

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Chia-Hung Kuo ,  Anoop Mukker ,  Eng Hun Ooi ,  Avishay Snir ,  Shrinivas Venkatraman ,  Kuan Hua Tan ,  Wai Ben Lin

IPC: G06F3/06

Abstract: A multi-level memory architecture scheme to dynamically balance a number of parameters such as power, thermals, cost, latency and performance for memory levels that are progressively further away from the processor in the platform based on how applications are using memory levels that are further away from processor cores. In some examples, the decision making for the state of the far memory (FM) is decentralized. For example, a processor power management unit (p-unit), near memory controller (NMC), and/or far memory host controller (FMHC) makes decisions about the power and/or performance state of the FM at their respective levels. These decisions are coordinated to provide the most optimum power and/or performance state of the FM for a given time. The power and/or performance state of the memories adaptively change to changing workloads and other parameters even when the processor(s) is in a particular power state.

公开(公告)号：US20190042155A1

公开(公告)日：2019-02-07

申请号：US15978766

申请日：2018-05-14

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Shrinivas Venkatraman ,  Kuan Hua Tan ,  Ang Li ,  Sahar Khalili ,  Su Wei Lim ,  Robert Royer, JR.

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/06

Abstract: Systems, apparatuses and methods may provide for technology to add non-address metadata to a memory address field of a transaction layer packet (TLP), wherein the non-address metadata includes one or more vendor-specific attributes. Additionally, the technology may coordinate between a transmitter and a receiver to prevent the TLP from violating an address boundary constraint associated with an interface. In one example, the address boundary constraint prohibits an address and length combination of the TLP from crossing a 4-KB boundary.

公开(公告)号：US11947995B2

公开(公告)日：2024-04-02

申请号：US16878064

申请日：2020-05-19

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Sahar Khalili ,  Eng Hun Ooi ,  Shrinivas Venkatraman ,  Dimpesh Patel

IPC: G06F9/54 ,  G06F9/46 ,  G06F11/30 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/467 ,  G06F9/546 ,  G06F11/3037 ,  G06F13/1668 ,  G06F13/385 ,  G06F13/4221 ,  G06F2213/0026 ,  G06F2213/3808

Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.

公开(公告)号：US09785604B2

公开(公告)日：2017-10-10

申请号：US13767881

申请日：2013-02-15

Applicant: Intel Corporation

Inventor： Ivan Herrera Mejia ,  Manuel A. Aguilar Arreola ,  Shrinivas Venkatraman ,  Andrea R. Vavra ,  Pavel Konev

IPC: G06F13/00 ,  G06F13/42 ,  G06F9/44 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F9/4411 ,  G06F13/385 ,  G06F13/4072 ,  G06F2213/0026

Abstract: Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some embodiments, performance of a link is evaluated at a plurality of equalization values and one of the plurality of equalization values is selected for the link based on comparison of a plurality of margin values that are to be determined for each of the plurality of equalization values. Other embodiments are also claimed and/or disclosed.