公开(公告)号：US20220057961A1

公开(公告)日：2022-02-24

申请号：US17519799

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Chetan CHAUHAN ,  Sourabh DONGAONKAR ,  Jawad B. KHAN

IPC: G06F3/06

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored physical one-bit wide columns with each bit of the multi-bit wide logical column stored in a one-bit physical column in a different physical die. The multi-bit column is read by reading a one-bit physical column in each of the different physical die in parallel. The multi-bit wide logical column is arranged diagonally across M physical rows and M one-bit physical columns with each bit of the multi-bit wide logical column in the logical row stored in a different physical row and physical one-bit wide column in one of plurality of dies.

公开(公告)号：US20210224267A1

公开(公告)日：2021-07-22

申请号：US17227045

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Jawad B. KHAN ,  Chetan CHAUHAN ,  Dipanjan SENGUPTA ,  Mariano TEPPER ,  Theodore WILLKE ,  Richard L. COULSON

IPC: G06F16/2458 ,  G06F16/248 ,  G06F16/21 ,  G06F16/22 ,  G06N7/00

Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.

公开(公告)号：US20220284948A1

公开(公告)日：2022-09-08

申请号：US17824808

申请日：2022-05-25

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Chetan CHAUHAN ,  Jawad B. KHAN ,  Rajesh SUNDARAM ,  Sandeep K. GULIANI

IPC: G11C11/4097 ,  G11C11/406

Abstract: Column read enabled three dimensional cross-point memory is optimized to reduce delay time due to partition busy times incurred when reading from a same partition. A column read enabled memory media stores each entry of a logical column of an array of bits in contiguous different physical rows and different physical columns of the cross-point memory array than any other entry of the logical column. Subsets of the contiguous different physical rows are stored in different partitions to reduce the delay time incurred when performing column reads from a same partition to improve media management operation performance.

公开(公告)号：US20210318805A1

公开(公告)日：2021-10-14

申请号：US17358222

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Jawad B. KHAN ,  Chetan CHAUHAN ,  Dipanjan SENGUPTA ,  Mariano TEPPER ,  Theodore WILLKE

IPC: G06F3/06 ,  G06K9/62

Abstract: Binary sparse encoding of data can be used to reduce an amount of data read from the stochastic associative memory while processing a query. Read performance of the stochastic associated memory is optimized to enhance the query throughput by modifying access patterns to reduce the time to read the stochastic associated memory. Read performance of the stochastic associative memory can be further improved through the use of cluster aware sharding and replication for parallelized similarity search. Clusters are partitioned across multiple Dual In-line Memory Modules (DIMMs), each DIMM including stochastic associative memory, to achieve maximum latency advantage.

公开(公告)号：US20210407564A1

公开(公告)日：2021-12-30

申请号：US17468210

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Chetan CHAUHAN ,  Jawad B. KHAN ,  Sandeep K. GULIANI ,  William K. WALLER

IPC: G11C7/10 ,  G11C5/02 ,  G11C5/14

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored in multi-bit wide columns in physically contiguous rows is provided. A multi-bit wide logical column is arranged diagonally across (M/multi-bits) physical rows and (M/multi-bits) physical columns with each of the plurality of multi-bit wide logical columns in the logical row stored in a different physical row and physical multi-bit column.

公开(公告)号：US20210294799A1

公开(公告)日：2021-09-23

申请号：US17341963

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： Wei WU ,  Sourabh DONGAONKAR ,  Jawad B. KHAN

IPC: G06F16/2458 ,  G06F16/248 ,  G06F16/22 ,  G06N3/04

Abstract: Methods and apparatus for sparse column-aware encodings for numeric data types, including integer data and floating-point data (float, double, etc.). The encoding schemes are tailored to take advantage of column addressable memories such as stochastic associative memories (SAM) to enable Stochastic Associative Search (SAS), which is a highly efficient and fast way of searching through a very large database of records (order of Billions) and finding similar records to a given query record (search key). Techniques are also disclosed for performing range searches for both integer and floating-point data types. The integer or float data is converted to Hexadecimal form and encoded using an m-of-n constant weight encoding. Only the columns with set bits in search keys need to be read, which significantly reduces the number of reads required for searches.

公开(公告)号：US20210286551A1

公开(公告)日：2021-09-16

申请号：US17337314

申请日：2021-06-02

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Jawad B. KHAN

IPC: G06F3/06

Abstract: Examples described herein relate to an apparatus comprising: circuitry to receive a request to store data as a part of a matrix in a memory device; circuitry to allocate address mappings to the data to reduce a number of sequential accesses to a same partition of a portion of the memory device; circuitry to store the address mappings for access with a read operation; and circuitry to cause storage of the data into the memory device according to the address mappings. In some examples, the matrix comprises one or more columns and/or one or more rows. In some examples, the memory device comprises one or more of: a three-dimensional (3D) cross point memory device, volatile memory device, or non-volatile memory device.