公开(公告)号：US20190096482A1

公开(公告)日：2019-03-28

申请号：US16140441

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Raymond W. ZENG ,  Mase J. TAUB ,  Kiran PANGAL ,  Sandeep K. GULIANI

IPC: G11C13/00 ,  G11C16/34 ,  G11C16/08 ,  G11C8/06

CPC classification number: G11C13/0028 ,  G11C8/06 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/3418 ,  G11C2013/0052 ,  G11C2013/0092

Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

公开(公告)号：US20200273508A1

公开(公告)日：2020-08-27

申请号：US16283128

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Balaji SRINIVASAN ,  Sandeep K. GULIANI ,  DerChang KAU ,  Ashir G. SHAH

IPC: G11C8/10 ,  G06F3/06

Abstract: A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.

公开(公告)号：US20220284948A1

公开(公告)日：2022-09-08

申请号：US17824808

申请日：2022-05-25

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Chetan CHAUHAN ,  Jawad B. KHAN ,  Rajesh SUNDARAM ,  Sandeep K. GULIANI

IPC: G11C11/4097 ,  G11C11/406

Abstract: Column read enabled three dimensional cross-point memory is optimized to reduce delay time due to partition busy times incurred when reading from a same partition. A column read enabled memory media stores each entry of a logical column of an array of bits in contiguous different physical rows and different physical columns of the cross-point memory array than any other entry of the logical column. Subsets of the contiguous different physical rows are stored in different partitions to reduce the delay time incurred when performing column reads from a same partition to improve media management operation performance.

公开(公告)号：US20170294228A1

公开(公告)日：2017-10-12

申请号：US15614141

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Mase J. TAUB ,  Sandeep K. GULIANI ,  Kiran PANGAL

IPC: G11C13/00 ,  G11C5/02

CPC classification number: G11C13/0004 ,  G11C5/02 ,  G11C7/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77

Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

公开(公告)号：US20210407564A1

公开(公告)日：2021-12-30

申请号：US17468210

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Chetan CHAUHAN ,  Jawad B. KHAN ,  Sandeep K. GULIANI ,  William K. WALLER

IPC: G11C7/10 ,  G11C5/02 ,  G11C5/14

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored in multi-bit wide columns in physically contiguous rows is provided. A multi-bit wide logical column is arranged diagonally across (M/multi-bits) physical rows and (M/multi-bits) physical columns with each of the plurality of multi-bit wide logical columns in the logical row stored in a different physical row and physical multi-bit column.

公开(公告)号：US20190074058A1

公开(公告)日：2019-03-07

申请号：US16105922

申请日：2018-08-20

Applicant: Intel Corporation

Inventor： Mase J. TAUB ,  Sandeep K. GULIANI ,  Kiran PANGAL

IPC: G11C13/00 ,  G11C7/00 ,  G11C5/02

Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.