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    Functionally redundant semiconductor dies and package
    1.
    发明授权
    Functionally redundant semiconductor dies and package 有权

    公开(公告)号：US11127712B2

    公开(公告)日：2021-09-21

    申请号：US15857731

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Wilfred Gomes ,  Mark T. Bohr ,  Udi Sherel ,  Leonard M. Neiberg ,  Nevine Nassif ,  Wesley D. McCullough

    IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00

    Abstract: Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

    Utilization of processor capacity at low operating frequencies
    4.
    发明授权
    Utilization of processor capacity at low operating frequencies 有权
    处理器容量在低工作频率下的利用率

    公开(公告)号：US09361234B2

    公开(公告)日：2016-06-07

    申请号：US14933378

    申请日：2015-11-05

    Applicant: Intel Corporation

    Inventor： Ruchira Sasanka ,  Alexander Gendler ,  Udi Sherel

    IPC: G06F1/32 ,  G06F12/02 ,  G06F12/08 ,  G06F1/26

    CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/324 ,  G06F12/0223 ,  G06F12/084 ,  G06F2212/62 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括一个或多个核，包括可在最小工作电压和最大工作电压之间的工作电压下工作的第一核。 处理器还包括功率控制单元，其包括第一逻辑，以便响应于小于或等于阈值电压的工作电压来使辅助逻辑耦合到第一核心，并且禁用辅助逻辑与第一核心的耦合响应 使工作电压大于阈值电压。 描述和要求保护其他实施例。

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