公开(公告)号：US20240105599A1

公开(公告)日：2024-03-28

申请号：US17955511

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Vishal TIWARI ,  Tahir GHANI ,  Mohit K. HARAN ,  Desalegne B. TEWELDEBRHAN

IPC: H01L23/528 ,  H01L29/423

CPC classification number: H01L23/528 ,  H01L29/4232

Abstract: Mushroomed via structures for trench contact or gate contact are described. In an example, an integrated circuit structure includes a trench contact structure over an epitaxial source or drain structure. A dielectric layer is over the trench contact structure. A trench contact via is in an opening in the dielectric layer, the trench contact via in contact with the trench contact structure. A trench contact via extension is on the trench contact via. The trench contact via extension above the dielectric layer and extending laterally beyond the trench contact via.

公开(公告)号：US20250006628A1

公开(公告)日：2025-01-02

申请号：US18216914

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Vishal TIWARI ,  Akm Shaestagir CHOWDHURY ,  Charles H. WALLACE

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a conductive via in a first dielectric layer. The integrated circuit structure also includes a conductive line in a second dielectric layer, the conductive including a conductive liner having a conductive barrier therein, the conductive barrier having a conductive fill therein, wherein the conductive liner is directly on the conductive via.

公开(公告)号：US20230420361A1

公开(公告)日：2023-12-28

申请号：US17852028

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Nita CHANDRASEKHAR ,  Vishal TIWARI ,  AKM Shaestagir CHOWDHURY

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76879 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76822

Abstract: Embodiments disclosed herein include integrated circuit structures and methods of forming such structures. In an embodiment, an integrated circuit structure comprises a dielectric layer with a first surface and a second surface, and an opening through the dielectric layer. In an embodiment, the opening is defined by sidewalls. In an embodiment, a graphene liner contacts the first surface of the dielectric layer and the sidewalls of the opening. In an embodiment, a conductive material at least partially fills a remainder of the opening.

公开(公告)号：US20210408282A1

公开(公告)日：2021-12-30

申请号：US16912103

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Vishal TIWARI ,  Rishabh MEHANDRU ,  Dan S. LAVRIC ,  Michal MLECZKO ,  Szuya S. LIAO

IPC: H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51

Abstract: Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.