公开(公告)号：US20190302379A1

公开(公告)日：2019-10-03

申请号：US16317796

申请日：2016-07-14

Applicant: Intel Corporation

Inventor： Vivek RAGHUNATHAN ,  Myung Jin YIM

IPC: G02B6/42 ,  H01L25/16

Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.

公开(公告)号：US20240353631A1

公开(公告)日：2024-10-24

申请号：US18761456

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Vivek RAGHUNATHAN ,  Myung Jin YIM

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/132 ,  H01L25/16

CPC classification number: G02B6/4206 ,  G02B6/122 ,  G02B6/132 ,  G02B6/42 ,  G02B6/4212 ,  G02B6/4225 ,  G02B6/428 ,  H01L25/167

Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.

公开(公告)号：US20200176272A1

公开(公告)日：2020-06-04

申请号：US16325100

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Vivek RAGHUNATHAN ,  Yonggang LI

IPC: H01L21/48 ,  H01L23/498

Abstract: Embodiments include methods for selective electroless plating of dielectric layers and devices formed by such processes. According to an embodiment, patterned surfaces are formed in a dielectric layer that includes metallic ceramic fillers. In some embodiments, the patterned surfaces form a line opening and a via opening that exposes a conductive pad. In an embodiment, the metallic ceramic fillers are activated to form activated surfaces over the patterned surfaces. A first metal is then deposited into the via opening with a first electroless solution that is a bottom-up deposition process. Thereafter, embodiments include forming a seed layer over exposed portions of the activated surfaces. In an embodiment, mid-gap states of the activated surfaces have an energy level approximately equal to a reduction potential of metal ions in a second electroless solution. Embodiments may then include depositing a second metal into the via opening with a third electroless solution.

公开(公告)号：US20180329240A1

公开(公告)日：2018-11-15

申请号：US15774432

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Vivek RAGHUNATHAN ,  Mihir K. ROY ,  Ravindranath V. MAHAJAN

IPC: G02F1/13357 ,  H05K1/18 ,  H05K1/02 ,  H05K3/30 ,  H01S3/04

CPC classification number: G02F1/1336 ,  G02F2001/133628 ,  G06F1/20 ,  H01S3/0408 ,  H04B1/38 ,  H04B1/385 ,  H05K1/0203 ,  H05K1/181 ,  H05K3/303 ,  H05K2201/10121 ,  H05K2201/10522

Abstract: Embodiments are generally directed to a self-cooled laser integrated device and substrate architecture. An embodiment of a device includes a substrate or printed circuit board (PCB); a component coupled with the substrate or PCB, the component including an cooling agent on at least one side of the component; one or more laser sources, at least a first laser source of the one or more laser sources being implemented to direct laser light onto the cooling agent; and a controller to drive the laser source, wherein the cooling agent provides cooling for the component when the laser light is directed on the engineered cooling agent.

公开(公告)号：US20210405306A1

公开(公告)日：2021-12-30

申请号：US17474484

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Vivek RAGHUNATHAN ,  Myung Jin YIM

IPC: G02B6/42 ,  H01L25/16 ,  G02B6/132 ,  G02B6/122

Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.