公开(公告)号：US20240320161A1

公开(公告)日：2024-09-26

申请号：US18575832

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Kaijie Guo ,  Qianjun Xie ,  Weigang Li ,  Junyuan Wang ,  Ashok Raj ,  Zijuan Fan

IPC: G06F12/1045 ,  G06F9/30

CPC classification number: G06F12/1045 ,  G06F9/3016 ,  G06F2212/50

Abstract: Systems, methods, and apparatuses to support a device translation lookaside buffer pre-translation instruction are described. A hardware system includes an input/output device, an input/output memory controller to perform a direct memory access of a memory for the input/output device, and a processor core separate from the input/output device and comprising a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including one or more fields to identify a virtual address to physical address mapping for the input/output device in the memory, and an opcode to indicate an execution circuit is to store the virtual address to physical address mapping into a translation lookaside buffer within the input/output device, and the execution circuit to execute the decoded single instruction according to the opcode.

公开(公告)号：US20240036631A1

公开(公告)日：2024-02-01

申请号：US18038660

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Liang Ma ,  Ping Yu ,  Fan Zhang ,  Weigang Li ,  Xin Zheng ,  Xiao Long Ye

IPC: G06F1/3296 ,  H04L9/40

CPC classification number: G06F1/3296 ,  H04L63/0428

Abstract: Various systems and methods for implementing protocol state aware power management are described herein. A network interface device for implementing protocol state aware power management includes circuitry to provide a direct memory access interface; medium access control (MAC) circuitry to interface with a network; and control circuitry to: classify packets received at the MAC circuitry as packets used to open network connections or packets used to close network connections; maintain statistics of packets used to open network connections and packets used to close network connections; calculate a power hint based on the statistics of packets used to open connections and packets used to close network connections; and write a receive descriptor to a host memory using the direct memory access interface, the receive descriptor including a power hint field with the power hint, the power hint used by a host processor to scale processor power based on the power hint.

公开(公告)号：US11422944B2

公开(公告)日：2022-08-23

申请号：US16989667

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Kaijie Guo ,  Weigang Li ,  Junyuan Wang ,  Liang Ma ,  Maksim Lukoshkov ,  Yao Huo

IPC: G06F12/1009 ,  H04L61/2596 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/42

Abstract: Examples herein relate to a system that includes a first memory device; a second memory device; and an input-output memory management unit (IOMMU). The IOMMU can search for a virtual-to-physical address translation entry in a first table for a received virtual address and based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device and the second table is stored in the second memory device. In some examples, based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, a page table walk is performed to determine a virtual-to-physical address translation for the received virtual address. In some examples, the first table includes an IO translation lookaside buffer (IOTLB).

公开(公告)号：US20250110903A1

公开(公告)日：2025-04-03

申请号：US18978180

申请日：2024-12-12

Applicant: Intel Corporation

Inventor： Dongsheng Liang ,  Junyuan Wang ,  Xiaoyan Bo ,  Yuze Xiao ,  Haoxiang Sun ,  Weigang Li ,  Marian Horgan ,  Fei Wang ,  John J. Browne ,  Laurent Coquerel ,  Giovanni Cabiddu ,  Vijay Sundar Selvamani ,  Steven Linsell ,  Karthikeyan Gopal ,  Deepika Ranganatha

IPC: G06F13/28

Abstract: A hardware accelerator device is provided with accelerator hardware to perform dictionary compressions in hardware based on a request from an application executed by a processor device coupled to the hardware accelerator device to compress data for the application.

公开(公告)号：US20230216849A1

公开(公告)日：2023-07-06

申请号：US18008743

申请日：2021-07-07

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  Junyuan Wang ,  Kaijie Guo ,  Zijuan Fan ,  Weigang Li ,  Lihui Zhang

IPC: H04L9/40

CPC classification number: H04L63/0884 ,  H04L63/20

Abstract: Various examples of device and system implementations and methods for performing attestation delegation operations are disclosed. In an example, attestation operations are performed by a verifier, including: obtaining endorsement information for attestation of an entity; obtaining an appraisal policy for evaluation of attestation evidence for the attestation of the entity; determining, based on the endorsement information and the appraisal policy, that delegation to a delegate verifier entity is permitted to perform the attestation of the entity; and providing, to the delegate verifier entity, a delegation command to perform the attestation of the entity, wherein the delegation command authorizes the delegate verifier entity to perform attestation operations (e.g., verifier operations) for a domain of entities including the entity.

公开(公告)号：US20230185732A1

公开(公告)日：2023-06-15

申请号：US18107399

申请日：2023-02-08

Applicant: Intel Corporation

Inventor： Weigang Li ,  Changzheng Wei ,  John Barry ,  Maryam Tahhan ,  Jonas Alexander Svennebring ,  Niall D. McDonnell ,  Alexander Leckey ,  Patrick Fleming ,  Christopher MacNamara ,  John Joseph Browne

IPC: G06F12/14 ,  G06F13/16 ,  G06F13/28 ,  G06F21/53 ,  G06F21/60 ,  G06F21/79

CPC classification number: G06F12/1408 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/53 ,  G06F21/602 ,  G06F21/606 ,  G06F21/79 ,  G06F2213/0038

Abstract: There is disclosed a computing apparatus, including: a memory; a memory encryption controller to encrypt at least a region of the memory; and a network interface to communicatively couple the computing apparatus to a remote host; wherein the memory encryption controller is configured to send an encrypted packet decryptable via an encryption key directly from the memory to the remote host via the network interface, bypassing a network protocol stack.

公开(公告)号：US20220244999A1

公开(公告)日：2022-08-04

申请号：US17724764

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Ned Smith ,  Changzheng Wei ,  Songwu Shen ,  Ziye Yang ,  Junyuan Wang ,  Weigang Li ,  Wenqian Yu

IPC: G06F9/50 ,  G06F21/76

Abstract: Technologies for hybrid field-programmable gate array (FPGA) application-specific integrated circuit (ASIC) code acceleration are described. In one example, the computing device includes a FPGA comprising: algorithm circuitry to: perform one or more algorithm tasks of an algorithm, wherein the algorithm to perform a service request that is offloaded to the FPGA; and determine a primitive task associated with an algorithm task of the one or more algorithm tasks; primitive offload circuitry to encapsulate the primitive task in a buffer of the FPGA, wherein the buffer is accessible by an ASIC of the computing device; and result circuitry to return one or more results of the service request responsive to performance of the primitive task by the ASIC.

公开(公告)号：US20210012035A1

公开(公告)日：2021-01-14

申请号：US16614236

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Changzheng Wei ,  Weigang Li ,  Cunming Liang

IPC: G06F21/78 ,  G06F21/44 ,  H04L9/08 ,  G06F21/76

Abstract: An embodiment of an electronic processing system may include a processor, persistent storage media communicatively coupled to the processor, a reconfigurable device communicatively coupled to the processor over a physically isolated trusted communication channel, a secure provisioner communicatively coupled to the processor and the reconfigurable device to provision a secure storage area and to securely store a remotely generated bitstream security key in the provisioned secure o storage area, and a device configurer to configure the reconfigurable device with a remotely generated bitstream and the remotely generated bitstream security key. Other embodiments are disclosed and claimed.

公开(公告)号：US20200371953A1

公开(公告)日：2020-11-26

申请号：US16989667

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Kaijie Guo ,  Weigang Li ,  Junyuan Wang ,  Liang Ma ,  Maksim Lukoshkov ,  Yao Huo

IPC: G06F12/1009 ,  H04L29/12 ,  G06F12/1027 ,  G06F13/42 ,  G06F13/28

Abstract: Examples herein relate to a system that includes a first memory device; a second memory device; and an input-output memory management unit (IOMMU). The IOMMU can search for a virtual-to-physical address translation entry in a first table for a received virtual address and based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device and the second table is stored in the second memory device. In some examples, based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, a page table walk is performed to determine a virtual-to-physical address translation for the received virtual address. In some examples, the first table includes an IO translation lookaside buffer (IOTLB).

公开(公告)号：US11805116B2

公开(公告)日：2023-10-31

申请号：US16957628

申请日：2018-03-31

Applicant: INTEL CORPORATION

Inventor： Changzheng Wei ,  Weigang Li ,  Danny Y. Zhou ,  Junyuan Wang ,  Hari K. Tadepalli ,  Rashmin N. Patel

IPC: H04W12/04 ,  H04W12/06 ,  H04L9/40 ,  H04W12/00 ,  H04L9/32 ,  G06F21/72

CPC classification number: H04L63/0823 ,  H04L9/3242 ,  H04L63/12 ,  H04W12/009 ,  H04L2463/062

Abstract: Technologies for securing a virtualization network function (VNF) image includes a security server to generate a wrapping cryptographic key to wrap a private key of the VNF image and replace the private key with the wrapped private key to secure the private key. During operation, the VNF image may be authenticated by a network function virtualization (NFV) server as needed. Additionally, the signature of the VNF image may be updated each time the VNF image is shutdown to ensure the continued authenticity of the VNF image.