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    TIMING COMPENSATION FOR A TIMESTAMP COUNTER
    3.
    发明申请
    TIMING COMPENSATION FOR A TIMESTAMP COUNTER 审中-公开

    公开(公告)号：US20190042295A1

    公开(公告)日：2019-02-07

    申请号：US16024554

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Liang Ma ,  John Joseph Browne ,  Xuebin Yang ,  Tomasz Kantecki ,  Andrew J. Herdrich

    IPC: G06F9/455

    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a request for a timestamp associated with a virtual machine, determine a current time from a timestamp counter, and subtract a timing compensation from the current time from the timestamp counter to create the timestamp, where the timing compensation includes an amount of time that execution of the virtual machine was suspended. In an example, a VM_EXIT instruction was used to suspend execution of the virtual machine and the timestamp counter was read before the VM_EXIT instruction was processed by a hypervisor.

    ADDRESS TRANSLATION TECHNOLOGIES
    6.
    发明申请
    ADDRESS TRANSLATION TECHNOLOGIES 审中-公开

    公开(公告)号：US20200371953A1

    公开(公告)日：2020-11-26

    申请号：US16989667

    申请日：2020-08-10

    Applicant: Intel Corporation

    Inventor： Kaijie Guo ,  Weigang Li ,  Junyuan Wang ,  Liang Ma ,  Maksim Lukoshkov ,  Yao Huo

    IPC: G06F12/1009 ,  H04L29/12 ,  G06F12/1027 ,  G06F13/42 ,  G06F13/28

    Abstract: Examples herein relate to a system that includes a first memory device; a second memory device; and an input-output memory management unit (IOMMU). The IOMMU can search for a virtual-to-physical address translation entry in a first table for a received virtual address and based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device and the second table is stored in the second memory device. In some examples, based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, a page table walk is performed to determine a virtual-to-physical address translation for the received virtual address. In some examples, the first table includes an IO translation lookaside buffer (IOTLB).

    TECHNOLOGIES FOR SCALABLE NETWORK PACKET PROCESSING WITH LOCK-FREE RINGS
    7.
    发明申请
    TECHNOLOGIES FOR SCALABLE NETWORK PACKET PROCESSING WITH LOCK-FREE RINGS 审中-公开

    公开(公告)号：US20190007330A1

    公开(公告)日：2019-01-03

    申请号：US15635581

    申请日：2017-06-28

    Applicant: Intel Corporation

    Inventor： John J. Browne ,  Tomasz Kantecki ,  Chris Macnamara ,  Pierre Laurent ,  Sean Harte ,  Peter McCarthy ,  Jacqueline F. Jardim ,  Liang Ma

    IPC: H04L12/873 ,  H04L12/883 ,  H04L12/879 ,  H04L12/927

    Abstract: Technologies for network packet processing include a computing device that receives incoming network packets. The computing device adds the incoming network packets to an input lockless shared ring, and then classifies the network packets. After classification, the computing device adds the network packets to multiple lockless shared traffic class rings, with each ring associated with a traffic class and output port. The computing device may allocate bandwidth between network packets active during a scheduling quantum in the traffic class rings associated with an output port, schedule the network packets in the traffic class rings for transmission, and then transmit the network packets in response to scheduling. The computing device may perform traffic class separation in parallel with bandwidth allocation and traffic scheduling. In some embodiments, the computing device may perform bandwidth allocation and/or traffic scheduling on each traffic class ring in parallel. Other embodiments are described and claimed.

    PROTOCOL STATE AWARE POWER MANAGEMENT
    8.
    发明公开
    PROTOCOL STATE AWARE POWER MANAGEMENT 审中-公开

    公开(公告)号：US20240036631A1

    公开(公告)日：2024-02-01

    申请号：US18038660

    申请日：2020-12-24

    Applicant: Intel Corporation

    Inventor： Liang Ma ,  Ping Yu ,  Fan Zhang ,  Weigang Li ,  Xin Zheng ,  Xiao Long Ye

    IPC: G06F1/3296 ,  H04L9/40

    CPC classification number: G06F1/3296 ,  H04L63/0428

    Abstract: Various systems and methods for implementing protocol state aware power management are described herein. A network interface device for implementing protocol state aware power management includes circuitry to provide a direct memory access interface; medium access control (MAC) circuitry to interface with a network; and control circuitry to: classify packets received at the MAC circuitry as packets used to open network connections or packets used to close network connections; maintain statistics of packets used to open network connections and packets used to close network connections; calculate a power hint based on the statistics of packets used to open connections and packets used to close network connections; and write a receive descriptor to a host memory using the direct memory access interface, the receive descriptor including a power hint field with the power hint, the power hint used by a host processor to scale processor power based on the power hint.

    Address translation technologies
    10.
    发明授权
    Address translation technologies 有权

    公开(公告)号：US11422944B2

    公开(公告)日：2022-08-23

    申请号：US16989667

    申请日：2020-08-10

    Applicant: Intel Corporation

    Inventor： Kaijie Guo ,  Weigang Li ,  Junyuan Wang ,  Liang Ma ,  Maksim Lukoshkov ,  Yao Huo

    IPC: G06F12/1009 ,  H04L61/2596 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/42

    Abstract: Examples herein relate to a system that includes a first memory device; a second memory device; and an input-output memory management unit (IOMMU). The IOMMU can search for a virtual-to-physical address translation entry in a first table for a received virtual address and based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device and the second table is stored in the second memory device. In some examples, based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, a page table walk is performed to determine a virtual-to-physical address translation for the received virtual address. In some examples, the first table includes an IO translation lookaside buffer (IOTLB).

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