公开(公告)号：US20230082780A1

公开(公告)日：2023-03-16

申请号：US17471889

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Chenmin SUN ,  Yipeng WANG ,  Rahul R. SHAH ,  Ren WANG ,  Sameh GOBRIEL ,  Hongjun NI ,  Mrittika GANGULI ,  Edwin VERPLANKE

IPC: G06F9/50

Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.

公开(公告)号：US20190004709A1

公开(公告)日：2019-01-03

申请号：US15639821

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Yipeng WANG ,  Ren WANG ,  Sameh GOBRIEL ,  Tsung-Yuan Charlie TAI

IPC: G06F3/06 ,  G06F12/128

Abstract: Examples may include techniques to control an insertion ratio or rate for a cache. Examples include comparing cache miss ratios for different time intervals or windows for a cache to determine whether to adjust a cache insertion ratio that is based on a ratio of cache misses to cache insertions.

公开(公告)号：US20220114270A1

公开(公告)日：2022-04-14

申请号：US17560193

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Ren WANG ,  Sameh GOBRIEL ,  Somnath PAUL ,  Yipeng WANG ,  Priya AUTEE ,  Abhirupa LAYEK ,  Shaman NARAYANA ,  Edwin VERPLANKE ,  Mrittika GANGULI ,  Jr-Shian TSAI ,  Anton SOROKIN ,  Suvadeep BANERJEE ,  Abhijit DAVARE ,  Desmond KIRKPATRICK

IPC: G06F21/62

Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

公开(公告)号：US20200371914A1

公开(公告)日：2020-11-26

申请号：US16986094

申请日：2020-08-05

Applicant: Intel Corporation

Inventor： Ren WANG ,  Yifan YUAN ,  Yipeng WANG ,  Tsung-Yuan C. TAI ,  Tony HURSON

IPC: G06F12/0804 ,  G06F16/23 ,  G06F13/16

Abstract: Examples described herein relates to a network interface apparatus that includes packet processing circuitry and a bus interface. In some examples, the packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write the data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory. In some examples, the packet processing circuitry is to issue a command to an input output (IO) controller to cause the IO controller to write the data to the cache and the non-volatile memory. In some examples, the cache comprises one or more of: a level-0 (L0), level-1 (L1), level-2 (L2), or last level cache (LLC) and the non-volatile memory comprises one or more of: volatile memory that is part of an Asynchronous DRAM Refresh (ADR) domain, persistent memory, battery-backed memory, or memory device whose state is determinate even if power is interrupted to the memory device. In some examples, based on receipt of a second received packet that includes a request to persist data, the packet processing circuitry is to request that data stored in a memory buffer be copied to the non-volatile memory.

公开(公告)号：US20200097269A1

公开(公告)日：2020-03-26

申请号：US16142401

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Yipeng WANG ,  Ren WANG ,  Tsung-Yuan C. TAI ,  Jr-Shian TSAI ,  Xiangyang GUO

IPC: G06F8/41 ,  G06F9/455

Abstract: Examples may include a method of compiling a declarative language program for a virtual switch. The method includes parsing the declarative language program, the program defining a plurality of match-action tables (MATs), translating the plurality of MATs into intermediate code, and parsing a core identifier (ID) assigned to each one of the plurality of MATs. When the core IDs of the plurality of MATs are the same, the method includes connecting intermediate code of the plurality of MATs using function calls, and translating the intermediate code of the plurality of MATs into machine code to be executed by a core identified by the core IDs.

公开(公告)号：US20220222118A1

公开(公告)日：2022-07-14

申请号：US17710594

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Ren WANG ,  Christian MACIOCCO ,  Yipeng WANG ,  Kshitij A. DOSHI ,  Vesh Raj SHARMA BANJADE ,  Satish C. JHA ,  S M Iftekharul ALAM ,  Srikathyayani SRIKANTESWARA ,  Alexander BACHMUTSKY

IPC: G06F9/50 ,  G06F13/42 ,  G06F12/1045

Abstract: Methods, apparatus, and systems for adaptive collaborative memory with the assistance of programmable networking devices. Under one example, the programmable networking device is a switch that is deployed in a system or cluster of servers comprising a plurality of nodes. The switch selects one or more nodes to be remote memory server nodes and allocate one or more portions of memory on those nodes to be used as remote memory for one or more remote memory client nodes. The switch receives memory access request messages originating from remote memory client nodes containing indicia identifying memory to be accessed, determines which remote memory server node is to be used for servicing a given memory access request, and sends a memory access request message containing indicia identifying memory to be accessed to the remote memory server node that is determined. The switch also facilitates return of messages containing remote memory access responses to the client nodes.

公开(公告)号：US20210089216A1

公开(公告)日：2021-03-25

申请号：US17099653

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Yipeng WANG ,  Ren WANG ,  Sameh GOBRIEL ,  Tsung-Yuan C. TAI

IPC: G06F3/06 ,  G06F12/128 ,  H04L12/747 ,  G06F12/0875

Abstract: Examples may include techniques to control an insertion ratio or rate for a cache. Examples include comparing cache miss ratios for different time intervals or windows for a cache to determine whether to adjust a cache insertion ratio that is based on a ratio of cache misses to cache insertions.

公开(公告)号：US20190102346A1

公开(公告)日：2019-04-04

申请号：US16207065

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Ren WANG ,  Andrew J. HERDRICH ,  Tsung-Yuan C. TAI ,  Yipeng WANG ,  Raghu KONDAPALLI ,  Alexander BACHMUTSKY ,  Yifan YUAN

IPC: G06F16/901 ,  G06F16/903

Abstract: A central processing unit can offload table lookup or tree traversal to an offload engine. The offload engine can provide hardware accelerated operations such as instruction queueing, bit masking, hashing functions, data comparisons, a results queue, and a progress tracking. The offload engine can be associated with a last level cache. In the case of a hash table lookup, the offload engine can apply a hashing function to a key to generate a signature, apply a comparator to compare signatures against the generated signature, retrieve a key associated with the signature, and apply the comparator to compare the key against the retrieved key. Accordingly, a data pointer associated with the key can be provided in the result queue. Acceleration of operations in tree traversal and tuple search can also occur.