公开(公告)号：US20220116045A1

公开(公告)日：2022-04-14

申请号：US17559569

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Mahesh K. Kumashikar ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Atul Maheshwari ,  Yuet Li ,  Mahesh A. Iyer

IPC: H03K19/17736 ,  H03K19/1776 ,  H03K19/17784

Abstract: An integrated circuit device that includes programmable logic circuitry that includes a plurality of regions each configured to operate at different voltage levels. The regions may be separated by level shifters that enable communication between the different voltage level regions. The integrated circuitry may also include software that performs voltage aware placement and routing for a user register-transfer level design, and may direct logic to regions according to voltages defined for the regions.

公开(公告)号：US12273107B2

公开(公告)日：2025-04-08

申请号：US17559831

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Atul Maheshwari ,  Mahesh Iyer ,  Mahesh K. Kumashikar ,  Ian Kuon ,  Yuet Li ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: H03K19/177 ,  G06F30/34

Abstract: Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

公开(公告)号：US20220116042A1

公开(公告)日：2022-04-14

申请号：US17559831

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Atul Maheshwari ,  Mahesh Iyer ,  Mahesh K. Kumashikar ,  Ian Kuon ,  Yuet Li ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: H03K19/177

Abstract: Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

公开(公告)号：US20220116038A1

公开(公告)日：2022-04-14

申请号：US17559350

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Mahesh K. Kumashikar ,  MD Altaf Hossain ,  Yuet Li ,  Atul Maheshwari ,  Ankireddy Nalamalpu

IPC: H03K19/00

Abstract: Systems or methods described herein may relate to latch-independent clock gating techniques to enable or disable an internal clock of an integrated circuit device. A programmable logic device includes a clock gating circuit that receives a clock signal and is latch independent. The clock gating circuit includes gating signal circuitry that generates a gating signal based on the clock signal and an enable signal. The clock gating circuit also includes a logic gate that generates a control signal based on the gating signal. The clock gating circuit also includes gated clock generation circuitry that generates a gated clock signal based on the clock signal and the control signal.

公开(公告)号：US20220114316A1

公开(公告)日：2022-04-14

申请号：US17559607

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Yuet Li ,  Ankireddy Nalamalpu ,  Atul Maheshwari ,  MD Altaf Hossain ,  Mahesh K. Kumashikar ,  Mahesh A. Iyer

IPC: G06F30/343 ,  G06F1/26

Abstract: Systems or methods of the present disclosure may provide for determining a loadline for operation of a programmable logic fabric where the loadline is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The loadline may be determined using software modeling for the design or configuration. Additionally or alternatively, the loadline may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

公开(公告)号：US20220113694A1

公开(公告)日：2022-04-14

申请号：US17559360

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Mahesh K. Kumashikar ,  MD Altaf Hossain ,  Mahesh A. Iyer ,  Yuet Li ,  Atul Maheshwari ,  Ankireddy Nalamalpu

IPC: G05B19/042

Abstract: Systems or methods of the present disclosure may provide efficient power consumption for programmable logic devices based on reducing guardband voltages. A programmable logic device may include circuit monitors to mimic critical paths of an implemented circuit design and generate timing information based on the critical paths. A controller on the programmable logic device may adjust the voltage guardband based on the timing information.