公开(公告)号：US20210281253A1

公开(公告)日：2021-09-09

申请号：US16474564

申请日：2017-03-29

Applicant: Intel IP Corporation

Inventor： Michael Kalcher ,  Daniel Gruber ,  Francesco Conzatti ,  Patrizia Greco

IPC: H03K5/00

Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.

公开(公告)号：US11323102B2

公开(公告)日：2022-05-03

申请号：US16474564

申请日：2017-03-29

Applicant: Intel IP Corporation

Inventor： Michael Kalcher ,  Daniel Gruber ,  Francesco Conzatti ,  Patrizia Greco

IPC: H03K5/00

Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.

公开(公告)号：US10148278B2

公开(公告)日：2018-12-04

申请号：US15863487

申请日：2018-01-05

Applicant: Intel IP Corporation

Inventor： Marco Bresciani ,  John G. Kauffman ,  Udo Schuetz ,  Patrick Torta ,  Francesco Conzatti

IPC: H03M1/00 ,  H03M1/10 ,  H03M3/00 ,  H03M1/46

Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.

公开(公告)号：US20180183452A1

公开(公告)日：2018-06-28

申请号：US15863487

申请日：2018-01-05

Applicant: Intel IP Corporation

Inventor： Marco Bresciani ,  John G. Kauffman ,  Udo Schuetz ,  Patrick Torta ,  Francesco Conzatti

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/46 ,  H03M3/386 ,  H03M3/424 ,  H03M3/454 ,  H03M3/464

Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.

公开(公告)号：US09866227B1

公开(公告)日：2018-01-09

申请号：US15391599

申请日：2016-12-27

Applicant: Intel IP Corporation

Inventor： Marco Bresciani ,  John G. Kauffman ,  Udo Schuetz ,  Patrick Torta ,  Francesco Conzatti

IPC: H03M1/00 ,  H03M1/10 ,  H03M1/46 ,  H03M3/00

CPC classification number: H03M1/1009 ,  H03M1/46 ,  H03M3/386 ,  H03M3/424 ,  H03M3/454 ,  H03M3/464

Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.