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11 条记录 (耗时 0.025 秒)

    Temperature dependent regulation of threshold voltage
    2.
    发明授权
    Temperature dependent regulation of threshold voltage 失效
    温度依赖调节阈值电压

    公开(公告)号：US06917237B1

    公开(公告)日：2005-07-12

    申请号：US10792262

    申请日：2004-03-02

    申请人： James W. Tschanz ,  Mircea R. Stan ,  Siva G. Narendra ,  Vivek K. De

    发明人： James W. Tschanz ,  Mircea R. Stan ,  Siva G. Narendra ,  Vivek K. De

    IPC分类号： G05F3/20 ,  G05F3/26 ,  H03K3/01

    CPC分类号： G05F3/262 ,  G05F3/205

    摘要： Embodiments circuits provide a transistor body bias voltage so that the ratio of ION to IOFF is constant over a range of temperature, where ION is a transistor current when ON and IOFF is a (leakage) transistor current when OFF. In one embodiment, a nFET is biased to provide ION to a current mirror that sources a current AION to a node, a nFET is biased to provide IOFF to a current mirror that sinks a current BIOFF from the node, and an amplifier provides feedback from the node to the body terminals of the nFETs so that at steady state AION=BIOFF, where A and B are constants independent over a range of temperature. In this way, the ratio ION/IOFF is maintained at B/A for some range of temperatures. Other embodiments are described and claimed.

    摘要翻译： 实施例电路提供晶体管体偏置电压，使得I ON / OFF与I OFF之间的比率在温度范围内是恒定的，其中I < 是ON时的晶体管电流，当OFF时，I 是晶体管电流（泄漏）。 在一个实施例中，nFET被偏置以将电流镜提供给电流反射镜，该电流镜将节点的当前AI导通，nFET被偏置以提供I < OFF 到从节点吸收当前BI OFF的电流镜，并且放大器从节点向nFET的体式终端提供反馈，使得在稳态AI ​​< ON = BI ，其中A和B在温度范围内是常数独立的。 以这种方式，在一些温度范围内，比率I ON / OFF / OFF保持在B / A。 描述和要求保护其他实施例。

    Dynamic CMOS circuits with individually adjustable noise immunity
    3.
    发明授权
    Dynamic CMOS circuits with individually adjustable noise immunity 有权
    动态CMOS电路具有独立可调的抗噪声能力

    公开(公告)号：US06710627B2

    公开(公告)日：2004-03-23

    申请号：US10322934

    申请日：2002-12-18

    申请人： Mircea R. Stan ,  Vivek K. De

    发明人： Mircea R. Stan ,  Vivek K. De

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： A technique to individually adjust noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network includes identifying precharge nodes of the dynamic circuit that require a reduction of noise. The technique further includes identifying NMOS transistor drains connected to respective precharge nodes, and creating a pull-up network of PMOS transistors for the identified precharge nodes. After creating a pull-up network of PMOS transistors, the technique includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve noise immunity and performance of the dynamic circuit. After arranging the order of the PMOS transistors, the technique can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes.

    摘要翻译： 单独调整包括并联或串并联下拉网络的动态电路的每个输入的噪声抗扰度的技术包括识别需要降低噪声的动态电路的预充电节点。 该技术还包括识别连接到相应预充电节点的NMOS晶体管漏极，以及为所识别的预充电节点创建PMOS晶体管的上拉网络。 在创建PMOS晶体管的上拉网络之后，该技术包括布置与各个预充电节点相对应的PMOS晶体管的阶数，以提高动态电路的抗噪声性能和性能。 在布置PMOS晶体管的顺序之后，该技术可以进一步包括对PMOS晶体管进行尺寸调整以实现预充电节点所需的噪声降低。

    Dynamic CMOS circuits with individually adjustable noise immunity
    4.
    发明授权
    Dynamic CMOS circuits with individually adjustable noise immunity 失效
    动态CMOS电路具有独立可调的抗噪声能力

    公开(公告)号：US06518796B1

    公开(公告)日：2003-02-11

    申请号：US09607495

    申请日：2000-06-30

    申请人： Mircea R. Stan ,  Vivek K. De

    发明人： Mircea R. Stan ,  Vivek K. De

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： A system of individually adjusting noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network comprises identifying precharge nodes of the dynamic circuit requiring a reduction of noise. Then further identifying NMOS transistor drains connected to the respective precharge nodes, then creating a pull-up network of PMOS transistors for the precharge nodes, respectively. After creating a pull-up network of PMOS transistors, the system further includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve the noise immunity and performance of the dynamic circuit. After completing the arranging of the order of the PMOS transistors, the system can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes, respectively.

    摘要翻译： 包括并行或串联并联下拉网络的动态电路的每个输入的单独调节噪声抗扰度的系统包括识别要求降低噪声的动态电路的预充电节点。 然后进一步识别连接到各个预充电节点的NMOS晶体管漏极，然后分别为预充电节点创建PMOS晶体管的上拉网络。 在创建PMOS晶体管的上拉网络之后，该系统还包括布置与各个预充电节点相对应的PMOS晶体管的阶数，以提高动态电路的抗噪声性能和性能。 在完成了PMOS晶体管的顺序排列之后，系统还可以包括分别对PMOS晶体管进行尺寸调整以实现预充电节点所需的噪声减小。

    Magnetic random access memory device
    6.
    发明授权
    Magnetic random access memory device 有权
    磁性随机存取存储器件

    公开(公告)号：US08953366B2

    公开(公告)日：2015-02-10

    申请号：US13697092

    申请日：2011-05-11

    申请人： Stuart A. Wolf ,  Jiwei Lu ,  Mircea R. Stan

    发明人： Stuart A. Wolf ,  Jiwei Lu ,  Mircea R. Stan

    IPC分类号： G11C11/00 ,  G11C11/14

    CPC分类号： G11C11/14 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/49069

    摘要： The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to each memory domain allowing the magnetization of the memory domain to be changed using a spin torque current, and ensuring the stability of the magnetization of the domain when it is not being written. The domain boundary between the memory domain and one of its adjacent fixed domains may thereby be moved. An antiferromagnetic element may be disposed proximate to each fixed domain to ensure the stability of the magnetization of these. The value of each memory domain may be read by applying a voltage to a magnetic tunnel junction comprising the memory domain and measuring the current flowing through it.

    摘要翻译： 本发明提出了一种包括存储器线的电子存储器件，该存储器线包括存储器域。 存储器线可以包含多个存储器域和多个固定域，其中每个存储器域存储单个二进制位值。 可以将多层元件设置在每个存储器域附近，从而允许使用自旋转矩电流来改变存储器域的磁化，并且当未写入时确保该域的磁化的稳定性。 因此，可以移动存储器域与其一个相邻固定域之间的域边界。 反铁磁元件可以设置在每个固定结构域附近，以确保这些磁化的稳定性。 可以通过将电压施加到包括存储器域的磁性隧道结并测量流过它的电流来读取每个存储器域的值。

    Method and system for encoding to eliminate parasitics in crossbar array memories
    7.
    发明授权
    Method and system for encoding to eliminate parasitics in crossbar array memories 有权
    用于编码的方法和系统，以消除交叉列阵列存储器中的寄生效应

    公开(公告)号：US08000161B2

    公开(公告)日：2011-08-16

    申请号：US12165281

    申请日：2008-06-30

    申请人： Mircea R. Stan ,  Adam C. Cabe

    发明人： Mircea R. Stan ,  Adam C. Cabe

    IPC分类号： G11C7/00

    CPC分类号： G11C13/00 ,  B82Y10/00 ,  G11C7/1006 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2207/102 ,  G11C2213/77 ,  G11C2213/81

    摘要： A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of ‘1’ bits and ‘0’ bits, and stores the modified words together with information enabling the original data to be retrieved upon being read out from memory.

    摘要翻译： 编码存储在诸如纳米线交叉开关存储器阵列的横向存储器阵列中的数据的编码方法能够显着增加存储器大小，将数据字修改为具有相等数量的“1”位和“0”位，并存储修改后的 单词与信息一起使得能够在从存储器读出时检索原始数据。

    Monolithically-Integrated Graphene-Nano-Ribbon (GNR) Devices, Interconnects and Circuits
    8.
    发明申请
    Monolithically-Integrated Graphene-Nano-Ribbon (GNR) Devices, Interconnects and Circuits 审中-公开
    单片集成石墨烯纳米带（GNR）器件，互连和电路

    公开(公告)号：US20090174435A1

    公开(公告)日：2009-07-09

    申请号：US12243165

    申请日：2008-10-01

    申请人： Mircea R. Stan ,  Avik Ghosh

    发明人： Mircea R. Stan ,  Avik Ghosh

    IPC分类号： H03K19/094 ,  H01L29/12 ,  H03K19/20

    CPC分类号： H03K19/02 ,  B82Y10/00 ,  H01L27/11803 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/7781 ,  H01L29/78684

    摘要： The invention discloses new and advantageous uses for carbon/graphene nanoribbons (GNRs), which includes, but is not limited to, electronic components for integrated circuits such as NOT gates, OR gates, AND gates, nano-capacitors, and other transistors. More specifically, the manipulation of the shapes, sizes, patterns, and edges, including doping profiles, of GNRs to optimize their use in various electronic devices is disclosed.

    摘要翻译： 本发明公开了用于碳/石墨烯纳米带（GNR）的新的和有利的用途，其包括但不限于用于诸如非门，或门，AND门，纳米电容器和其它晶体管的集成电路的电子部件。 更具体地，公开了GNR的形状，尺寸，图案和边缘（包括掺杂分布）的操纵以优化其在各种电子设备中的使用。

    SYSTEM, METHOD, AND COMPUTER READABLE MEDIUM FOR WALKING PADS: FAST POWER-SUPPLY PAD-PLACEMENT OPTIMIZATION
    9.
    发明申请
    SYSTEM, METHOD, AND COMPUTER READABLE MEDIUM FOR WALKING PADS: FAST POWER-SUPPLY PAD-PLACEMENT OPTIMIZATION 审中-公开
    系统，方法和计算机可读介质：快速供电贴片优化

    公开(公告)号：US20160210392A1

    公开(公告)日：2016-07-21

    申请号：US15000826

    申请日：2016-01-19

    申请人： Ke Wang ,  Kevin Skadron ,  Mircea R. Stan ,  Runjie Zhang ,  Brett Meyer

    发明人： Ke Wang ,  Kevin Skadron ,  Mircea R. Stan ,  Runjie Zhang ,  Brett Meyer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5036 ,  G06F17/504 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/08 ,  G06F2217/78

    摘要： A virtual force controlled collapse chip connection (C4) pad placement optimization frame-work for 2D power delivery grids is proposed. The present optimization framework regards power pads as mobile “positive charged particles” and current resources as a “negative charged back-ground.” The virtual electrostatic force is calculated from voltage gradients. This optimization framework optimizes pad locations by moving pads according to the virtual forces exerted on them by other pads and current sources in the system. Within this framework, three algorithms are proposed to meet various requirements of optimization quality and speed. These algorithms minimize resistive voltage drop (IR drop), the maximum current density, and power distribution network metal power dissipation at the same time.

    摘要翻译： 提出了一种用于2D功率输送网格的虚拟力控制崩溃芯片连接（C4）焊盘放置优化框架。 目前的优化框架将电源板作为移动“正带电粒子”和当前资源作为“负电荷背景”。虚拟静电力由电压梯度计算。 该优化框架通过根据系统中其他焊盘和电流源施加在其上的虚拟力移动焊盘来优化焊盘位置。 在此框架内，提出了三种算法，以满足优化质量和速度的各种要求。 这些算法同时最大限度地降低了电阻电压降（IR drop），最大电流密度和配电网络金属功耗。

    MAGNETIC RANDOM ACCESS MEMORY DEVICE
    10.
    发明申请
    MAGNETIC RANDOM ACCESS MEMORY DEVICE 有权
    磁性随机访问存储器件

    公开(公告)号：US20130058157A1

    公开(公告)日：2013-03-07

    申请号：US13697092

    申请日：2011-05-11

    申请人： Stuart A. Wolf ,  Jiwei Lu ,  Mircea R. Stan

    发明人： Stuart A. Wolf ,  Jiwei Lu ,  Mircea R. Stan

    IPC分类号： G11C11/16 ,  G11C99/00

    CPC分类号： G11C11/14 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/49069

    摘要： The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to each memory domain allowing the magnetization of the memory domain to be changed using a spin torque current, and ensuring the stability of the magnetization of the domain when it is not being written. The domain boundary between the memory domain and one of its adjacent fixed domains may thereby be moved. An antiferromagnetic element may be disposed proximate to each fixed domain to ensure the stability of the magnetization of these. The value of each memory domain may be read by applying a voltage to a magnetic tunnel junction comprising the memory domain and measuring the current flowing through it.

    摘要翻译： 本发明提出了一种包括存储器线的电子存储器件，该存储器线包括存储器域。 存储器线可以包含多个存储器域和多个固定域，其中每个存储器域存储单个二进制位值。 可以将多层元件设置在每个存储器域附近，从而允许使用自旋转矩电流来改变存储器域的磁化，并且当未写入时确保该域的磁化的稳定性。 因此，可以移动存储器域与其一个相邻固定域之间的域边界。 反铁磁元件可以设置在每个固定结构域附近，以确保这些磁化的稳定性。 可以通过将电压施加到包括存储器域的磁性隧道结并测量流过它的电流来读取每个存储器域的值。