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公开(公告)号：US20170192324A1
公开(公告)日：2017-07-06
申请号：US15467442
申请日：2017-03-23
Applicant: Japan Display Inc.
Inventor： Hiroaki KOMATSU , Takanori Nakayama , Saori Sugiyama
IPC: G02F1/1362 , G02F1/1337 , G02F1/1368 , G02F1/1343 , G02F1/1339
CPC classification number: G02F1/136227 , G02F1/133784 , G02F1/13394 , G02F1/134363 , G02F1/136286 , G02F1/1368 , G02F2001/136236 , G02F2201/121 , G02F2201/123 , G02F2201/14
Abstract: To provide a liquid crystal display device capable of controlling deterioration of contrast even in the case where an opening is formed in an organic flattened film and the film has unevenness. In the liquid crystal display device that includes a TFT substrate, a CF substrate, and liquid crystal sandwiched between the TFT substrate and the CF substrate and that drives the liquid crystal with a lateral electric field, the TFT substrate has the organic flattened film in which a through hole for contacting a source electrode of the TFT and a pixel electrode and a sectional shape of the through hole is asymmetrical between a side on which the pixel electrode extends and the other side.
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公开(公告)号：US20150124190A1
公开(公告)日：2015-05-07
申请号：US14532028
申请日：2014-11-04
Applicant: Japan Display Inc.
Inventor： Hiroaki KOMATSU , Takanori NAKAYAMA , Saori SUGIYAMA
IPC: G02F1/1343 , G02F1/1337 , G02F1/1339 , G02F1/1368 , G02F1/1362
CPC classification number: G02F1/136227 , G02F1/133784 , G02F1/13394 , G02F1/134363 , G02F1/136286 , G02F1/1368 , G02F2001/136236 , G02F2201/121 , G02F2201/123 , G02F2201/14
Abstract: To provide a liquid crystal display device capable of controlling deterioration of contrast even in the case where an opening is formed in an organic flattened film and the film has unevenness. In the liquid crystal display device that includes a TFT substrate, a CF substrate, and liquid crystal sandwiched between the TFT substrate and the CF substrate and that drives the liquid crystal with a lateral electric field, the TFT substrate has the organic flattened film in which a through hole for contacting a source electrode of the TFT and a pixel electrode and a sectional shape of the through hole is asymmetrical between a side on which the pixel electrode extends and the other side.
Abstract translation: 为了提供即使在有机平坦化膜中形成开口并且膜具有不均匀性的情况下也能够控制对比度降低的液晶显示装置。 在包含TFT基板，CF基板以及夹在TFT基板和CF基板之间并以横向电场驱动液晶的液晶的液晶显示装置中，TFT基板具有有机平坦化膜，其中， 用于接触TFT的源电极和像素电极的通孔和通孔的截面形状在像素电极延伸的一侧与另一侧之间是不对称的。
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公开(公告)号：US20140111757A1
公开(公告)日：2014-04-24
申请号：US14056019
申请日：2013-10-17
Applicant: JAPAN DISPLAY INC.
Inventor： Hiroaki KOMATSU , Saori SUGIYAMA
IPC: G02F1/1339
CPC classification number: G02F1/13394 , G02F1/136286 , G02F2001/13396
Abstract: A liquid crystal display device having 2 pixel multi-domain type pixels, in which columnar spacers are disposed in optimal positions. Each of plural video lines has a first portion in which an acute-angled crossing angle of two crossing angles crossing each of scanning lines becomes a positive angle in a clockwise direction from each of the scanning lines, and a second portion in which an acute-angled crossing angle of the two crossing angles crossing each of scanning lines becomes a negative angle in the clockwise direction from each of the scanning lines. The first and second portions are alternately disposed so as to hold the scanning line between them.
Abstract translation: 具有2像素多域型像素的液晶显示装置，其中柱状间隔件设置在最佳位置。 多个视频线中的每一条具有第一部分，其中与扫描线交叉的两个交叉角的锐角交叉角从每条扫描线沿顺时针方向成为正角度;第二部分， 与扫描线交叉的两个交叉角的角度交叉角从每条扫描线变为顺时针方向的负角度。 第一和第二部分交替地设置成在它们之间保持扫描线。
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公开(公告)号：US20180068631A1
公开(公告)日：2018-03-08
申请号：US15808142
申请日：2017-11-09
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hiroaki KOMATSU
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/2018 , G09G3/3674 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/28
Abstract: A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.
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公开(公告)号：US20150332645A1
公开(公告)日：2015-11-19
申请号：US14805134
申请日：2015-07-21
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hideo SATO , Hiroaki KOMATSU
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0248 , G09G2310/0251 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
Abstract translation: 栅极信号线驱动电路包括多个基本电路，每个基本电路向门信号线输出在高信号周期期间为高电平的栅极信号，并在低信号周期期间输出低电平。 每个基本电路包括：玛瑙线高压施加电路，根据高信号周期接通，将高电压施加到栅极信号线; 栅极线路低电压施加电路，其根据低信号周期接通，以将低电压施加到栅极信号线; 以及第二栅极线低电压施加电路，其在关闭栅极线高压应用电路和接通栅极线路的低电压应用之间的至少一部分周期中接通以将低电压施加到栅极信号线 电路。
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Patent Agency Ranking
公开(公告)号：US20170053614A1
公开(公告)日：2017-02-23
申请号：US15290009
申请日：2016-10-11
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hiroaki KOMATSU
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/2018 , G09G3/3674 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/28
Abstract: A driving circuit of a display device includes first to third output signal lines which are continuously arranged, a first transistor that has a source connected to the second output signal line and a drain connected to a first clock signal line, and a second transistor that provides a non-active potential to a gate of the first transistor when a second clock signal becomes the active potential, wherein a circuit that outputs the active potential to the first output signal line and the third output signal line is disposed at an opposite side to a circuit that outputs the active potential to the second output signal line with a display region interposed therebetween, and wherein the gate of the first transistor is connected to the first output signal line and the third output signal line via rectifying circuits.
Abstract translation: 显示装置的驱动电路包括连续布置的第一至第三输出信号线，具有连接到第二输出信号线的源极和连接到第一时钟信号线的漏极的第一晶体管和提供 当第二时钟信号变为有效电位时，对第一晶体管的栅极的非有效电位，其中向第一输出信号线和第三输出信号线输出有效电位的电路设置在与第 电路，其具有介于其间的显示区域向第二输出信号线输出有效电位，并且其中第一晶体管的栅极经由整流电路连接到第一输出信号线和第三输出信号线。
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公开(公告)号：US20160363798A1
公开(公告)日：2016-12-15
申请号：US15244751
申请日：2016-08-23
Applicant: JAPAN DISPLAY INC.
Inventor： Hiroaki KOMATSU , Saori SUGIYAMA
IPC: G02F1/1339 , G02F1/1362
CPC classification number: G02F1/13394 , G02F1/136286 , G02F2001/13396
Abstract: A liquid crystal display device having 2-pixel multi-domain type pixels, in which columnar spacers are disposed in optimal positions. Each of plural video lines has a first portion in which an acute-angled crossing angle of two crossing angles crossing each of scanning lines becomes a positive angle in a clockwise direction from each of the scanning lines, and a second portion in which an acute-angled crossing angle of the two crossing angles crossing each of scanning lines becomes a negative angle in the clockwise direction from each of the scanning lines. The first and second portions are alternately disposed so as to hold the scanning line between them.
Abstract translation: 具有2像素多畴型像素的液晶显示装置，其中柱状间隔件设置在最佳位置。 多个视频线中的每一条具有第一部分，其中与扫描线交叉的两个交叉角的锐角交叉角从每条扫描线沿顺时针方向成为正角度;第二部分， 与扫描线交叉的两个交叉角的角度交叉角从每条扫描线变为顺时针方向的负角度。 第一和第二部分交替地设置成在它们之间保持扫描线。
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公开(公告)号：US20190122629A1
公开(公告)日：2019-04-25
申请号：US16225094
申请日：2018-12-19
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hideo SATO , Hiroaki KOMATSU
CPC classification number: G09G3/3677 , G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0248 , G09G2310/0251 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
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公开(公告)号：US20180374444A1
公开(公告)日：2018-12-27
申请号：US16106835
申请日：2018-08-21
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hideo SATO , Hiroaki KOMATSU
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gats signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
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公开(公告)号：US20170076686A1
公开(公告)日：2017-03-16
申请号：US15361785
申请日：2016-11-28
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hideo SATO , Hiroaki KOMATSU
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0248 , G09G2310/0251 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: a gate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
Abstract translation: 栅极信号线驱动电路包括多个基本电路，每个基本电路向门信号线输出在高信号周期期间为高电平的栅极信号，并在低信号周期期间输出低电平。 每个基本电路包括：栅极线高电压施加电路，其根据高信号周期导通，以将高电压施加到栅极信号线; 栅极线路低电压施加电路，其根据低信号周期接通，以将低电压施加到栅极信号线; 以及第二栅极线低电压施加电路，其在关闭栅极线高压应用电路和接通栅极线路的低电压应用之间的至少一部分周期中接通以将低电压施加到栅极信号线 电路。
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