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57 条记录 (耗时 0.031 秒)

    Chip to chip interface for interconnecting chips
    1.
    发明授权
    Chip to chip interface for interconnecting chips 失效
    用于互连芯片的芯片到芯片接口

    公开(公告)号：US06910092B2

    公开(公告)日：2005-06-21

    申请号：US10016800

    申请日：2001-12-10

    申请人： Jean Louis Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Joseph Franklin Logan ,  Tolga Ozguner

    发明人： Jean Louis Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Joseph Franklin Logan ,  Tolga Ozguner

    IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F13/42

    CPC分类号： G06F13/4265

    摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.

    摘要翻译： 网络处理器（NP）由多个可操作耦合的芯片形成。 NP包括耦合到耦合到数据流芯片的数据流芯片和数据存储存储器的网络处理器复合（NPC）芯片。 可选的调度器芯片耦合到数据流芯片。 命名的组件被复制以创建对称的入口和出口结构。 芯片之间的通信由一对芯片到芯片宏提供，其中每一个可操作地位于一个芯片上，并且芯片到芯片总线接口可操作地将芯片连接到芯片宏。

    Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus
    2.
    发明授权
    Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus 失效
    用于实现点对点总线的多个可配置子总线的方法和装置

    公开(公告)号：US06996650B2

    公开(公告)日：2006-02-07

    申请号：US10147682

    申请日：2002-05-16

    申请人： Jean Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Christopher Jon Johnson ,  Joseph Franklin Logan ,  Tolga Ozguner

    发明人： Jean Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Christopher Jon Johnson ,  Joseph Franklin Logan ,  Tolga Ozguner

    IPC分类号： G06F13/42 ,  G06F13/14 ,  G06F13/40

    CPC分类号： G06F13/4273 ,  G06F13/4059

    摘要： A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.

    摘要翻译： 提供了一种用于实现点对点总线的多个可配置子总线的方法和装置。 多个总线互连中的每一个包括连接到点对点总线的发送接口和接收接口。 每个发送接口包括耦合在缓冲器和点到点总线之间的发送缓冲器和串行器。 发送缓冲区提供发送源和串行器之间的异步接口。 串行器以第一频率从发送缓冲器接收数据和控制信号，并以更高的第二频率在点对点总线上发送数据和控制信号。 发射导向逻辑耦合在多个总线互连的发射源和每个发射缓冲器之间。 发射导向逻辑基于所选择的总线配置将数据和控制信号从发射源引导到每个所选发射缓冲器中的一个。

    Network processor with single interface supporting tree search engine and CAM
    5.
    发明授权
    Network processor with single interface supporting tree search engine and CAM 失效
    具有单界面支持树搜索引擎和CAM的网络处理器

    公开(公告)号：US07953077B2

    公开(公告)日：2011-05-31

    申请号：US11457952

    申请日：2006-07-17

    申请人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    发明人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

    摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

    摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

    Network processor with single interface supporting tree search engine and CAM
    6.
    发明授权
    Network processor with single interface supporting tree search engine and CAM 失效
    具有单界面支持树搜索引擎和CAM的网络处理器

    公开(公告)号：US07167471B2

    公开(公告)日：2007-01-23

    申请号：US09940758

    申请日：2001-08-28

    申请人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    发明人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

    摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

    摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

    System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory
    8.
    发明申请
    System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory 审中-公开
    具有由具有分布式片上共享存储器和外部共享存储器的片上网络链接的可编程处理元件阵列的片上系统

    公开(公告)号：US20100191911A1

    公开(公告)日：2010-07-29

    申请号：US12639325

    申请日：2009-12-16

    申请人： Marco Heddes ,  Massimo Ravasi ,  Rakesh Kumar Malik ,  Timothy M. Shanley ,  Michael Singngee Yeo

    发明人： Marco Heddes ,  Massimo Ravasi ,  Rakesh Kumar Malik ,  Timothy M. Shanley ,  Michael Singngee Yeo

    IPC分类号： G06F15/80 ,  G06F9/06 ,  G06F12/08 ,  G06F12/02

    CPC分类号： G06F15/16

    摘要： An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon.

    摘要翻译： 具有可编程处理元件阵列的集成电路和由片上通信网络链接的存储器接口。 每个处理元件包括多个处理核心和本地存储器。 存储器接口块可操作地耦合到外部存储器和片上通信网络。 存储器接口支持通过片上通信网络响应于从阵列的处理元件传送的消息来访问外部存储器。 阵列的多个处理元件的一部分本地存储器的一部分以及外部存储器的一部分都被分配以在执行分配在其上的编程操作期间存储由阵列的多个处理元件共享的数据。

    SYSTEM FOR MANAGING MULTI-FIELD CLASSIFICATION RULES RELATING TO INGRESS CONTEXTS AND EGRESS CONTEXTS
    9.
    发明申请
    SYSTEM FOR MANAGING MULTI-FIELD CLASSIFICATION RULES RELATING TO INGRESS CONTEXTS AND EGRESS CONTEXTS 失效
    用于管理与生态系统和排气系统有关的多领域分类规则的系统

    公开(公告)号：US20080249973A1

    公开(公告)日：2008-10-09

    申请号：US12143641

    申请日：2008-06-20

    申请人： Everett A. Corl ,  Gordon T. Davis ,  Marco Heddes ,  Piyush C. Patel ,  Ravinder K. Sabhikhi

    发明人： Everett A. Corl ,  Gordon T. Davis ,  Marco Heddes ,  Piyush C. Patel ,  Ravinder K. Sabhikhi

    IPC分类号： G06N5/02

    CPC分类号： G06N99/005

    摘要： The present invention relates to a system for managing a plurality of multi-field classification rules. The system provides a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The system also includes a network processor for classifying packets of information, wherein the network processor is programmed to utilize the first table and the second table to identify any rules relating to the ingress context and any one rules relating to the egress context that match a search key.

    摘要翻译： 本发明涉及一种用于管理多个多场分类规则的系统。 该系统提供第一表，其包括对应于与入口上下文相关的多个规则的多个条目，以及第二表，其包括对应于与出口上下文相关的多个规则的多个条目。 该系统还包括用于对信息包进行分类的网络处理器，其中网络处理器被编程为利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索匹配的出口上下文相关的任何规则 键。

    Method for managing multi-field classification rules relating to ingress
    10.
    发明授权
    Method for managing multi-field classification rules relating to ingress 失效
    管理与入口有关的多领域分类规则的方法

    公开(公告)号：US07412431B2

    公开(公告)日：2008-08-12

    申请号：US10832958

    申请日：2004-04-27

    申请人： Everett A. Corl, Jr. ,  Gordon T. Davis ,  Marco Heddes ,  Piyush C. Patel ,  Ravinder K. Sabhikhi

    发明人： Everett A. Corl, Jr. ,  Gordon T. Davis ,  Marco Heddes ,  Piyush C. Patel ,  Ravinder K. Sabhikhi

    IPC分类号： G06F17/00 ,  G06N5/02

    CPC分类号： G06N99/005

    摘要： The present invention relates to a method for managing a plurality of multi-field classification rules. The method includes providing a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and providing a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The method also includes utilizing the first table and the second table to identify any rules relating to the ingress context and any rules relating to the egress context that match a search key.

    摘要翻译： 本发明涉及一种用于管理多个多场分类规则的方法。 该方法包括提供第一表格，该第一表格包括对应于与入口上下文有关的多个规则的多个条目，并提供第二表格，该第二表格包括对应于与出口上下文有关的多个规则的多个条目。 该方法还包括利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索关键字匹配的出口上下文相关的任何规则。