公开(公告)号：US06819723B1

公开(公告)日：2004-11-16

申请号：US09327178

申请日：1999-06-07

申请人： Jieh-Tsorng Wu ,  Hsi-Yuan Wang

发明人： Jieh-Tsorng Wu ,  Hsi-Yuan Wang

IPC分类号： H04L27156

CPC分类号： H03D3/06 ,  H04L27/156

摘要： A digital FM demodulator utilizes delay lines as the timing reference and incorporates the concept of delta-sigma analog-to-digital conversion to implement the function of time-to-digital conversion. The FM demodulator is constructed from delay lines, a multiplexer, a phase detector, a charge pump circuit, a quantizer and a digital integrator. The modulated signal on an intermediate frequency carrier passes through the delay lines and is then phase-compared with the original modulation signal. The comparison produces a pulse which is converted into a voltage and stored in a capacitor by way of the charge pump circuit. The voltage having been accumulated and quantized, a new delayed output signal is acquired to compare its phase with the input signal. Meanwhile, the phase difference between input signal and delayed signal is used to select a delay for the delayed signal for the next cycle. The phase difference is continuously evaluated and adjusted to produce zero phase difference. The digital modulation signal is collected at the system output.

摘要翻译： 数字FM解调器利用延迟线作为定时参考，并结合了delta-sigma模数转换的概念来实现时间到数字转换的功能。 FM解调器由延迟线，多路复用器，相位检测器，电荷泵电路，量化器和数字积分器构成。 中频载波上的调制信号通过延迟线，然后与原始调制信号进行相位比较。 该比较产生脉冲，该脉冲通过电荷泵电路转换成电压并存储在电容器中。 已经累积和量化的电压，获得新的延迟输出信号以将其相位与输入信号进行比较。 同时，输入信号和延迟信号之间的相位差用于为下一个周期的延迟信号选择延迟。 相位差被连续评估和调整以产生零相位差。 数字调制信号在系统输出端收集。

公开(公告)号：US20120229315A1

公开(公告)日：2012-09-13

申请号：US13339978

申请日：2011-12-29

申请人： Wei-Hsin Tseng ,  Jieh-Tsorng Wu

发明人： Wei-Hsin Tseng ,  Jieh-Tsorng Wu

IPC分类号： H03M1/80

CPC分类号： H03M1/0641 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

摘要： An N-bit digital-to-analog converting device includes: a decoder for converting an N-bit binary digital signal into a multi-bit thermometer code during each cycle of a clock signal alternating between first and second states, N being an integer not less than two; a random number generator for generating a reset signal having at least one high logic level bit and at least one low logic level bit that are equal in number and that have a random, time-varying arrangement; and a converting module coupled electrically to the decoder and the random number generator, and configured to convert the thermometer code into an analog voltage corresponding to the digital signal when the clock signal is in the first state, and to reset the analog voltage to a reset value according to the reset signal when the clock signal is in the second state.

摘要翻译： N位数模转换装置包括：解码器，用于在第一和第二状态之间交替的时钟信号的每个周期期间将N位二进制数字信号转换成多位温度计代码，N是不整数的整数 小于二; 随机数发生器，用于产生具有至少一个高逻辑电平位和至少一个低逻辑电平位的复位信号，所述至少一个低逻辑电平位的数量相等并且具有随机的时变布置; 以及转换模块，其电耦合到所述解码器和所述随机数发生器，并且被配置为当所述时钟信号处于所述第一状态时将所述温度计代码转换成对应于所述数字信号的模拟电压，并且将所述模拟电压复位为复位 当时钟信号处于第二状态时根据复位信号计算值。

公开(公告)号：US07821435B2

公开(公告)日：2010-10-26

申请号：US12424286

申请日：2009-04-15

申请人： Jen-Lin Fan ,  Jieh-Tsorng Wu

发明人： Jen-Lin Fan ,  Jieh-Tsorng Wu

IPC分类号： H03M1/00

CPC分类号： H03M1/1004 ,  H03M1/1042 ,  H03M1/12

摘要： The present invention discloses a background calibration system and method for calibrating the non-linear distortion of the amplifier. The calibration method in the present invention includes: generating random sequences and inputting the random sequences in different amount and different sets into an amplifier; amplifying the random sequences and detecting linear and non-linear coefficients; quantizing the output linear signal from the amplifier, and generating a digital output signal; multiplying the digital output signal to generate a high-order signal; generating an estimated non-linear error for the amplifier by multiplying the high-order signal with the estimated non-linear coefficient; adding the non-linear signal with the digital output signal to generate a linear output signal; calculating the random value from the parameter extractor to determine the occurrence of non-linear distortion in the circuit, and further adjusting the non-linear coefficient to calibrating the amplifier.

摘要翻译： 本发明公开了一种用于校准放大器的非线性失真的背景校准系统和方法。 本发明的校准方法包括：生成随机序列，并将不同数量和不同组的随机序列输入放大器; 放大随机序列并检测线性和非线性系数; 量化来自放大器的输出线性信号，并产生数字输出信号; 将数字输出信号相乘以产生高阶信号; 通过将高阶信号与估计的非线性系数相乘来产生放大器的估计的非线性误差; 用数字输出信号加上非线性信号以产生线性输出信号; 从参数提取器计算随机值以确定电路中非线性失真的发生，并进一步调整非线性系数以校准放大器。

公开(公告)号：US08493253B2

公开(公告)日：2013-07-23

申请号：US13339978

申请日：2011-12-29

申请人： Wei-Hsin Tseng ,  Jieh-Tsorng Wu

发明人： Wei-Hsin Tseng ,  Jieh-Tsorng Wu

IPC分类号： H03M1/66

CPC分类号： H03M1/0641 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

摘要： An N-bit digital-to-analog converting device includes: a decoder for converting an N-bit binary digital signal into a multi-bit thermometer code during each cycle of a clock signal alternating between first and second states, N being an integer not less than two; a random number generator for generating a reset signal having at least one high logic level bit and at least one low logic level bit that are equal in number and that have a random, time-varying arrangement; and a converting module coupled electrically to the decoder and the random number generator, and configured to convert the thermometer code into an analog voltage corresponding to the digital signal when the clock signal is in the first state, and to reset the analog voltage to a reset value according to the reset signal when the clock signal is in the second state.

摘要翻译： N位数模转换装置包括：解码器，用于在第一和第二状态之间交替的时钟信号的每个周期期间将N位二进制数字信号转换成多位温度计代码，N是不整数的整数 小于二; 随机数发生器，用于产生具有至少一个高逻辑电平位和至少一个低逻辑电平位的复位信号，所述至少一个低逻辑电平位的数量相等并且具有随机的时变布置; 以及转换模块，其电耦合到所述解码器和所述随机数发生器，并且被配置为当所述时钟信号处于所述第一状态时将所述温度计代码转换成对应于所述数字信号的模拟电压，并且将所述模拟电压复位为复位 当时钟信号处于第二状态时根据复位信号计算值。

公开(公告)号：US20080180136A1

公开(公告)日：2008-07-31

申请号：US11715476

申请日：2007-03-08

申请人： Jieh-Tsorng Wu ,  Zwei-Mei Lee ,  Cheng-Yeh Wang

发明人： Jieh-Tsorng Wu ,  Zwei-Mei Lee ,  Cheng-Yeh Wang

IPC分类号： G11C27/02

CPC分类号： G11C27/026

摘要： A precharge sample-and-hold circuit is formed by coupling a buffer with an input port and making use of a switch to conduct the circuit between the buffer and a total load capacitor for precharging according the state of a sample-and-hold circuit. When the sample-and-hold circuit is in the sample mode, it precharges the total load capacitor. When the sample-and-hold circuit is in the hold mode, the influence to the sampled signal is further reduced due to the precharging. The requirements of swing rate, output voltage swing, gain-bandwidth product for the opamps can therefore be reduced, hence being applicable to the realization of the design of advanced fabrication technologies of low supply voltages.

摘要翻译： 通过将缓冲器与输入端口耦合并利用开关来根据取样保持电路的状态将缓冲器和总负载电容器之间的电路进行预充电来形成预充电采样和保持电路。 当采样保持电路处于采样模式时，它将对负载电容器进行预充电。 当采样保持电路处于保持模式时，由于预充电，对采样信号的影响进一步减小。 因此，可以减小运算放大器的摆幅，输出电压摆幅，增益带宽乘积的要求，因此适用于实现低电源电压的先进制造技术的设计。

公开(公告)号：US5438621A

公开(公告)日：1995-08-01

申请号：US857924

申请日：1992-05-05

申请人： Thomas Hornak ,  Patrick Petruno ,  Richard C. Walker ,  Benny W. H. Lai ,  Chu-Sun Yen ,  Cheryl L. Stout ,  Jieh-Tsorng Wu

发明人： Thomas Hornak ,  Patrick Petruno ,  Richard C. Walker ,  Benny W. H. Lai ,  Chu-Sun Yen ,  Cheryl L. Stout ,  Jieh-Tsorng Wu

IPC分类号： H03M5/14 ,  H04J3/06 ,  H04J3/12 ,  H04L7/04 ,  H04L25/49

CPC分类号： H04J3/12 ,  H03M5/145 ,  H04J3/0602 ,  H04L25/4915 ,  H04L2007/045

摘要： A method of encoding data for transmission over a communication link. A cumulative polarity of previously-transmitted frames is maintained. A frame is prepared for transmission by combining a data word with a plurality of additional bits. The additional bits provide a master transition. A phantom bit is encoded in the additional bits. If the polarity of the frame is the same as the cumulative polarity, the data bits or in some instances all the bits are inverted so as to maintain balance. Control words and fill words are provided and are distinguished from data words by encoding the additional bits. Control words carry additional data or control instructions and are distinguished from fill words by the number of transitions. The phantom bit either conveys additional data or is used for such purposes as error checking.

摘要翻译： PCT No.PCT / US91 / 08483 Sec。 371日期：1992年5月5日 102（e）日期1992年5月5日PCT 1991年11月13日PCT PCT。 出版物WO92 / 09162 日期：1992年5月29日。一种对通过通信链路传输的数据进行编码的方法。 维持先前传输的帧的累积极性。 通过组合数据字与多个附加位来准备用于发送的帧。 附加位提供主转换。 幻像位被编码在附加位中。 如果帧的极性与累积极性相同，则数据位或在某些情况下所有位都被反转，以保持平衡。 提供控制字和填充字，并通过编码附加位与数据字区分开。 控制字携带附加数据或控制指令，并且通过转换次数与填充字区分开。 幻影位传送附加数据或用于错误检查等目的。

公开(公告)号：US07243277B2

公开(公告)日：2007-07-10

申请号：US11183601

申请日：2005-07-18

申请人： Jieh-Tsorng Wu ,  Ta-Hui Wang ,  Hsie-Chia Chang

发明人： Jieh-Tsorng Wu ,  Ta-Hui Wang ,  Hsie-Chia Chang

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C29/00 ,  G11C29/42

摘要： A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.

摘要翻译： 存储器组合用于存储数据的多个存储单元，其中存储单元的差分级电压电平不受2的平方值的限制，并且可以线性地改善。 本发明的特征还可以增加存储容量而不增加存储区。 此外，当读取数据时，它可以保持不能表示错误消除消息的0和1组合的电压电平。 为了有效利用存储器，增加的存储器容量不仅用于存储数据，而且用于存储纠错方案以确保存储数据的真实性，并提高多级存储器系统的产量和可靠性。

公开(公告)号：US07064693B1

公开(公告)日：2006-06-20

申请号：US11135218

申请日：2005-05-23

申请人： Chun-Cheng Huang ,  Jieh-Tsorng Wu

发明人： Chun-Cheng Huang ,  Jieh-Tsorng Wu

IPC分类号： H03M1/10

CPC分类号： H03F3/45973 ,  H03M1/1004 ,  H03M1/36

摘要： A background-calibrated comparator and a background-calibrated flash analog-to-digital converter are disclosed for using in mixed-signal integrated circuit design in particular on the high-speed analog-to-digital converter circuit. Without affecting the operation of the comparator, the disclosure is directed at reducing the unpredictable input offset voltage originated from the variation of process parameters and environmental factors. The background-calibrated comparator includes a random chopping comparator, a calibration processor, and a random sequence generator. The background-calibrated flash analog-to-digital converter (ADC) includes a background-calibrated comparator array together with a reference voltage generator, a thermometer code edge detector, and a set of digital encoders.

摘要翻译： 公开了背景校准的比较器和背景校准的闪存模数转换器，用于在混合信号集成电路设计中，特别是在高速模数转换器电路上使用。 不影响比较器的操作，本公开旨在减少源自工艺参数和环境因素变化的不可预测的输入偏移电压。 背景校准的比较器包括随机斩波比较器，校准处理器和随机序列发生器。 背景校准的闪存模数转换器（ADC）包括背景校准的比较器阵列以及参考电压发生器，温度计码边缘检测器和一组数字编码器。

公开(公告)号：US20060015793A1

公开(公告)日：2006-01-19

申请号：US11183601

申请日：2005-07-18

申请人： Jieh-Tsorng Wu ,  Ta-Hui Wang ,  Hsie-Chia Chang

发明人： Jieh-Tsorng Wu ,  Ta-Hui Wang ,  Hsie-Chia Chang

IPC分类号： H03M13/00

CPC分类号： G11C29/44 ,  G11C29/00 ,  G11C29/42

摘要： A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.

摘要翻译： 存储器组合用于存储数据的多个存储单元，其中存储单元的差分级电压电平不受2的平方值的限制，并且可以线性地改善。 本发明的特征还可以增加存储容量而不增加存储区。 此外，当读取数据时，它可以保持不能表示错误消除消息的0和1组合的电压电平。 为了有效利用存储器，增加的存储器容量不仅用于存储数据，而且用于存储纠错方案以确保存储数据的真实性，并提高多级存储器系统的产量和可靠性。

公开(公告)号：US06777994B2

公开(公告)日：2004-08-17

申请号：US10271553

申请日：2002-10-17

申请人： Ju-Ming Chou ,  Yu-Tang Hsieh ,  Jieh-Tsorng Wu

发明人： Ju-Ming Chou ,  Yu-Tang Hsieh ,  Jieh-Tsorng Wu

IPC分类号： H03H1126

CPC分类号： H03K3/0322 ,  G06F1/04 ,  H03K5/133 ,  H03K2005/00208

摘要： To reduce the effect of the phase shift error originated from the mismatch of the delay units of the clock generator, we propose to add one more set of averaging amplifiers and averaging impedances, such as resistors, into the circuit of the clock generator. In the clock generator, outputs of all delay units connect to inputs of all averaging amplifiers respectively, and the averaging impedances connect the corresponding outputs of two adjacent averaging amplifiers, so as to form a closed loop. When a phase shift error occurs in the delay units, the averaging current through the averaging impedances will decrease the phase shift error in each stage. Specifically, the output impedance of the averaging amplifiers approaches infinite, and thus the resistance of the averaging impedances is relatively small. Therefore almost all signal currents will go through the averaging impedances, and an optimal averaging effect is achieved. In addition, we apply the simple voltage-mode phase interpolation technique to the averaging impedances for better phase resolution and more output phases. Further, utilizing the folding architecture, our proposed clock generator can output high-frequency clock signals at low-frequency operating clock.

摘要翻译： 为了减少源自时钟发生器的延迟单元不匹配的相移误差的影响，我们建议在时钟发生器的电路中增加一组平均放大器和平均阻抗（如电阻）。 在时钟发生器中，所有延迟单元的输出分别连接到所有平均放大器的输入，平均阻抗连接两个相邻平均放大器的相应输出，以形成闭环。 当在延迟单元中出现相移误差时，通过平均阻抗的平均电流将降低每个阶段的相移误差。 具体地，平均放大器的输出阻抗接近无穷大，因此平均阻抗的电阻相对较小。 因此，几乎所有的信号电流将经过平均阻抗，并且实现了最佳的平均效应。 此外，我们将简单的电压模式相位插值技术应用于平均阻抗，以获得更好的相位分辨率和更多的输出相位。 此外，利用折叠架构，我们提出的时钟发生器可以在低频工作时钟输出高频时钟信号。