公开(公告)号：US07498248B2

公开(公告)日：2009-03-03

申请号：US11590072

申请日：2006-10-31

申请人： Jung-Taek Lim ,  Dong-Chun Lee ,  Young-Jee Yoon ,  Sung-Hong Park

发明人： Jung-Taek Lim ,  Dong-Chun Lee ,  Young-Jee Yoon ,  Sung-Hong Park

IPC分类号： H01L21/3205

CPC分类号： G03F7/70633

摘要： In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure. A second conductive contact structure is formed at a position on a second semiconductor substrate that is determined in response to the determination of whether the first conductive contact structure is electrically connected to the conductive pattern structure.

摘要翻译： 在半导体衬底上的结构制造期间补偿对准误差的方法中，在第一半导体衬底上的第一位置处形成导电图案结构。 导电图案结构包括布置成列和相交行的第一和第二导电图案的格栅，其间具有开口。 第一导电接触结构与导电图案结构重叠，并且包括布置成可以相对于导电图案结构的格栅非零角度倾斜的行和列格栅的多个间隔开的导电接点。 确定第一导电接触结构是否电连接到导电图案结构。 第二导电接触结构形成在第二半导体衬底上的响应于第一导电接触结构是否电连接到导电图案结构的确定而确定的位置。

公开(公告)号：US20070120220A1

公开(公告)日：2007-05-31

申请号：US11590072

申请日：2006-10-31

申请人： Jung-Taek Lim ,  Dong-Chun Lee ,  Young-Jee Yoon ,  Sung-Hong Park

发明人： Jung-Taek Lim ,  Dong-Chun Lee ,  Young-Jee Yoon ,  Sung-Hong Park

IPC分类号： H01L29/00

CPC分类号： G03F7/70633

摘要： In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure. A second conductive contact structure is formed at a position on a second semiconductor substrate that is determined in response to the determination of whether the first conductive contact structure is electrically connected to the conductive pattern structure.

摘要翻译： 在半导体衬底上的结构制造期间补偿对准误差的方法中，在第一半导体衬底上的第一位置处形成导电图案结构。 导电图案结构包括布置成列和相交行的第一和第二导电图案的格栅，其间具有开口。 第一导电接触结构与导电图案结构重叠，并且包括布置成可以相对于导电图案结构的格栅非零角度倾斜的行和列格栅的多个间隔开的导电接点。 确定第一导电接触结构是否电连接到导电图案结构。 第二导电接触结构形成在第二半导体衬底上的响应于第一导电接触结构是否电连接到导电图案结构的确定而确定的位置。

公开(公告)号：US07626164B2

公开(公告)日：2009-12-01

申请号：US11564726

申请日：2006-11-29

申请人： Young-Jee Yoon ,  Jung-Taek Lim ,  Tae-Sung Kim ,  Chung-Sam Jun ,  Sung-Hong Park

发明人： Young-Jee Yoon ,  Jung-Taek Lim ,  Tae-Sung Kim ,  Chung-Sam Jun ,  Sung-Hong Park

IPC分类号： G01N23/00

CPC分类号： G01N23/203

摘要： In an embodiment, a method of scanning a substrate, and a method and an apparatus for analyzing crystal characteristics are disclosed. A sequential scan on the scan areas using a first electron beam and a second electron beam are repeatedly performed. The electrons accumulated in the scan areas by the first electron beam are removed from the scan areas by the second electron beam. When a size of the scan area is substantially the same as a spot size of the first electron beam, adjacent scan areas partially overlap each other. When each of the scan areas is larger than a spot size of the first electron beam, the adjacent scan areas do not overlap each other. Images of the scan areas are generated using back-scattered electrons emitted from each of the scan areas by irradiating the first electron beam to analyze crystal characteristics of circuit patterns on the substrate.

摘要翻译： 在一个实施例中，公开了一种扫描衬底的方法，以及用于分析晶体特性的方法和装置。 使用第一电子束和第二电子束对扫描区域进行顺序扫描。 通过第二电子束从扫描区域去除由第一电子束累积在扫描区域中的电子。 当扫描区域的尺寸与第一电子束的光斑尺寸基本相同时，相邻的扫描区域彼此部分重叠。 当每个扫描区域大于第一电子束的光斑尺寸时，相邻的扫描区域彼此不重叠。 通过照射第一电子束来分析从每个扫描区域发射的背散射电子来分析扫描区域的图像，以分析衬底上的电路图案的晶体特性。

公开(公告)号：US07747063B2

公开(公告)日：2010-06-29

申请号：US11463281

申请日：2006-08-08

申请人： Jung-Taek Lim ,  Chung-Sam Jun ,  Young-Jee Yoon ,  Sung-Hong Park

发明人： Jung-Taek Lim ,  Chung-Sam Jun ,  Young-Jee Yoon ,  Sung-Hong Park

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G06T2207/30148 ,  H01J2237/2817

摘要： In an embodiment of a method of inspecting a substrate, the substrate on which minute structures are formed is divided into a plurality of inspection regions. A main inspection region among the inspection regions is selected. A main image of the main inspection region and sub-images of sub-inspection regions adjacent to the main inspection region are obtained. An average image of the main image and the sub-images is obtained. The average image is then compared with the main image to detect defects in the main inspection region. Gray levels may be used. The average image may have improved quality so that the defects in the selected inspection region may be rapidly and accurately detected. This process has an improved reliability. Further, the number of inspecting processes for the substrate may be reduced. And a line for the inspection process may be automated so that a worker-free line may be established.

摘要翻译： 在检查基板的方法的实施例中，其上形成有微小结构的基板被分成多个检查区域。 选择检验区域的主要检验区域。 获得主检查区域的主要图像和与主检查区域相邻的副检查区域的子图像。 获得主图像和子图像的平均图像。 然后将平均图像与主图像进行比较，以检测主检查区域中的缺陷。 可以使用灰度级。 平均图像可以具有改进的质量，使得可以快速和准确地检测所选择的检查区域中的缺陷。 该过程具有改进的可靠性。 此外，可以减少基板的检查过程的数量。 并且检查过程的一行可以是自动化的，从而可以建立无工人行。

公开(公告)号：US20070031025A1

公开(公告)日：2007-02-08

申请号：US11463281

申请日：2006-08-08

申请人： Jung-Taek Lim ,  Chung-Sam Jun ,  Young-Jee Yoon ,  Sung-Hong Park

发明人： Jung-Taek Lim ,  Chung-Sam Jun ,  Young-Jee Yoon ,  Sung-Hong Park

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G06T2207/30148 ,  H01J2237/2817

摘要： In an embodiment of a method of inspecting a substrate, the substrate on which minute structures are formed is divided into a plurality of inspection regions. A main inspection region among the inspection regions is selected. A main image of the main inspection region and sub-images of sub-inspection regions adjacent to the main inspection region are obtained. An average image of the main image and the sub-images is obtained. The average image is then compared with the main image to detect defects in the main inspection region. Gray levels may be used. The average image may have improved quality so that the defects in the selected inspection region may be rapidly and accurately detected. This process has an improved reliability. Further, the number of inspecting processes for the substrate may be reduced. And a line for the inspection process may be automated so that a worker-free line may be established.

摘要翻译： 在检查基板的方法的实施例中，其上形成有微小结构的基板被分成多个检查区域。 选择检验区域的主要检验区域。 获得主检查区域的主要图像和与主检查区域相邻的副检查区域的子图像。 获得主图像和子图像的平均图像。 然后将平均图像与主图像进行比较，以检测主检查区域中的缺陷。 可以使用灰度级。 平均图像可以具有改进的质量，使得可以快速和准确地检测所选择的检查区域中的缺陷。 该过程具有改进的可靠性。 此外，可以减少基板的检查过程的数量。 并且检查过程的一行可以是自动化的，从而可以建立无工人行。

公开(公告)号：US20060029286A1

公开(公告)日：2006-02-09

申请号：US11198314

申请日：2005-08-08

申请人： Jung-Taek Lim ,  Hyo-Cheon Kang ,  Chung-Sam Jun ,  Dong-Chun Lee ,  Byoung-Ho Lee

发明人： Jung-Taek Lim ,  Hyo-Cheon Kang ,  Chung-Sam Jun ,  Dong-Chun Lee ,  Byoung-Ho Lee

IPC分类号： G06K9/40

CPC分类号： G06T5/50 ,  G01N23/225 ,  G06T5/002 ,  G06T5/003 ,  G06T5/20 ,  G06T2207/10061 ,  G06T2207/20032 ,  G06T2207/20192 ,  G06T2207/30148 ,  H01J2237/221 ,  H01J2237/2802

摘要： An image processing method is disclosed. The method comprises capturing a plurality of images of a sample using a scanning electron microscope (SEM). The method further comprising computing a mean value for each pixel location in the plurality of images and forming an integrated image with the mean values. The method further comprises filtering the integrated image using a median filter.

摘要翻译： 公开了一种图像处理方法。 该方法包括使用扫描电子显微镜（SEM）捕获样品的多个图像。 该方法还包括计算多个图像中的每个像素位置的平均值，并形成具有平均值的积分图像。 该方法还包括使用中值滤波器对集成图像进行滤波。

公开(公告)号：US06495055B2

公开(公告)日：2002-12-17

申请号：US09337735

申请日：1999-06-22

申请人： Jung-Taek Lim ,  Sung-Joon Byun ,  Soo-Won Lee ,  Jin-Soo Kim

发明人： Jung-Taek Lim ,  Sung-Joon Byun ,  Soo-Won Lee ,  Jin-Soo Kim

IPC分类号： C03C25068

CPC分类号： H01L21/67253 ,  C23F1/02 ,  C23F1/08

摘要： An etching system and method. In the method, layers are etched on a plurality of substrates using a single amount of etchant to form a predetermined pattern on each of the layers, wherein an etching period varies according to an accumulated process number of substrates. The system includes an etching equipment including an etching processor for etching layers on a plurality of substrates using a single amount of etchant to form a predetermined pattern on each of the layers, and a loader for temporarily holding cassettes in which the substrates are stored; and a controller for controlling operations of the etching equipment. The etching equipment changes an etching period according to an accumulated process number of the substrates.

摘要翻译： 蚀刻系统和方法。 在该方法中，使用单一量的蚀刻剂在多个基板上蚀刻层，以在每个层上形成预定图案，其中蚀刻周期根据累积的基板数量而变化。 该系统包括蚀刻设备，其包括用于使用单一量的蚀刻剂在多个基板上蚀刻层以在每个层上形成预定图案的蚀刻处理器，以及用于临时保持其中存储基板的盒的装载器; 以及用于控制蚀刻设备的操作的控制器。 蚀刻设备根据基板的累积处理次数改变蚀刻周期。