Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号:US07989988B2

    公开(公告)日:2011-08-02

    申请号:US12306500

    申请日:2006-06-30

    摘要: In a power phase period when in normal operation, switch portions SW2H and SW2L and switch portions SW3H and SW3L are turned ON, respectively, and switch portions SW1H and SW1L are turned OFF. And floating power supply is provided from an electrostatic capacitance element CS to buses A and B, a floating control circuit 4, a transmitter circuit 5, and a receiver circuit 6, respectively. In a data phase period, the switch portions SW1H and SW1L are turned ON, and the switch portions SW2H, SW2L, SW3H, and SW3L are turned OFF. By that manner, the electrostatic capacitance element CS is charged by the power supply of a battery B, and an electrostatic capacitance element CH provides the floating power supply to the floating control circuit 4, the transmitter circuit 5, and the receiver circuit 6, respectively. By this manner, a floating switch unit 7 in which the number of the switch portions is considerably reduced can be configured.

    摘要翻译: 在通常动作的电力相位期间,开关部SW2H,SW2L和开关部SW3H,SW3L分别导通,开关部SW1H,SW1L分别断开。 并且浮动电源分别从静电电容元件CS提供给总线A和B,浮动控制电路4,发送器电路5和接收器电路6。 在数据相位期间,开关部分SW1H和SW1L导通,开关部分SW2H,SW2L,SW3H和SW3L截止。 通过这种方式,静电电容元件CS由电池B的电源充电,并且静电电容元件CH分别向浮动控制电路4,发送器电路5和接收器电路6提供浮动电源 。 通过这种方式,可以构成开关部分的数目明显减少的浮动开关单元7。

    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号:US08093762B2

    公开(公告)日:2012-01-10

    申请号:US13178933

    申请日:2011-07-08

    摘要: In a power phase period when in normal operation, switch portions SW2H and SW2L and switch portions SW3H and SW3L are turned ON, respectively, and switch portions SW1H and SW1L are turned OFF. And floating power supply is provided from an electrostatic capacitance element CS to buses A and B, a floating control circuit 4, a transmitter circuit 5, and a receiver circuit 6, respectively. In a data phase period, the switch portions SW1H and SW1L are turned ON, and the switch portions SW2H, SW2L, SW3H, and SW3L are turned OFF. By that manner, the electrostatic capacitance element CS is charged by the power supply of a battery B, and an electrostatic capacitance element CH provides the floating power supply to the floating control circuit 4, the transmitter circuit 5, and the receiver circuit 6, respectively. By this manner, a floating switch unit 7 in which the number of the switch portions is considerably reduced can be configured.

    摘要翻译: 在通常动作的电力相位期间,开关部SW2H,SW2L和开关部SW3H,SW3L分别导通,开关部SW1H,SW1L分别断开。 并且浮动电源分别从静电电容元件CS提供给总线A和B,浮动控制电路4,发送器电路5和接收器电路6。 在数据相位期间,开关部分SW1H和SW1L导通,开关部分SW2H,SW2L,SW3H和SW3L截止。 由此,通过电池B的电源对静电电容元件CS进行充电,静电电容元件CH分别向浮动控制电路4,发送电路5和接收电路6提供浮动电源 。 通过这种方式,可以构成开关部分的数目明显减少的浮动开关单元7。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号:US20110260776A1

    公开(公告)日:2011-10-27

    申请号:US13178933

    申请日:2011-07-08

    IPC分类号: H03K17/687

    摘要: In a power phase period when in normal operation, switch portions SW2H and SW2L and switch portions SW3H and SW3L are turned ON, respectively, and switch portions SW1H and SW1L are turned OFF. And floating power supply is provided from an electrostatic capacitance element CS to buses A and B, a floating control circuit 4, a transmitter circuit 5, and a receiver circuit 6, respectively. In a data phase period, the switch portions SW1H and SW1L are turned ON, and the switch portions SW2H, SW2L, SW3H, and SW3L are turned OFF. By that manner, the electrostatic capacitance element CS is charged by the power supply of a battery B, and an electrostatic capacitance element CH provides the floating power supply to the floating control circuit 4, the transmitter circuit 5, and the receiver circuit 6, respectively. By this manner, a floating switch unit 7 in which the number of the switch portions is considerably reduced can be configured.

    摘要翻译: 在通常动作的电力相位期间,开关部SW2H,SW2L和开关部SW3H,SW3L分别导通,开关部SW1H,SW1L分别断开。 并且浮动电源分别从静电电容元件CS提供给总线A和B,浮动控制电路4,发送器电路5和接收器电路6。 在数据相位期间,开关部分SW1H和SW1L导通,开关部分SW2H,SW2L,SW3H和SW3L截止。 通过这种方式,静电电容元件CS由电池B的电源充电,并且静电电容元件CH分别向浮动控制电路4,发送器电路5和接收器电路6提供浮动电源 。 通过这种方式,可以构成开关部分的数目明显减少的浮动开关单元7。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
    半导体集成电路设备

    公开(公告)号:US20090200874A1

    公开(公告)日:2009-08-13

    申请号:US12306500

    申请日:2006-06-30

    IPC分类号: H02M3/06

    摘要: In a power phase period when in normal operation, switch portions SW2H and SW2L and switch portions SW3H and SW3L are turned ON, respectively, and switch portions SW1H and SW1L are turned OFF. And floating power supply is provided from an electrostatic capacitance element CS to buses A and B, a floating control circuit 4, a transmitter circuit 5, and a receiver circuit 6, respectively. In a data phase period, the switch portions SW1H and SW1L are turned ON, and the switch portions SW2H, SW2L, SW3H, and SW3L are turned OFF. By that manner, the electrostatic capacitance element CS is charged by the power supply of a battery B, and an electrostatic capacitance element CH provides the floating power supply to the floating control circuit 4, the transmitter circuit 5, and the receiver circuit 6, respectively. By this manner, a floating switch unit 7 in which the number of the switch portions is considerably reduced can be configured.

    摘要翻译: 在通常动作的电力相位期间,开关部SW2H,SW2L和开关部SW3H,SW3L分别导通,开关部SW1H,SW1L分别断开。 并且浮动电源分别从静电电容元件CS提供给总线A和B,浮动控制电路4,发送器电路5和接收器电路6。 在数据相位期间,开关部分SW1H和SW1L导通,开关部分SW2H,SW2L,SW3H和SW3L截止。 由此,通过电池B的电源对静电电容元件CS进行充电,静电电容元件CH分别向浮动控制电路4,发送电路5和接收电路6提供浮动电源 。 通过这种方式,可以构成开关部分的数目明显减少的浮动开关单元7。

    Lateral type transistor
    5.
    发明授权
    Lateral type transistor 失效
    横向晶体管

    公开(公告)号:US6060761A

    公开(公告)日:2000-05-09

    申请号:US48094

    申请日:1998-03-26

    CPC分类号: H01L29/735

    摘要: A lateral transistor includes a semiconductor substrate of a first conductivity type having a major surface; an emitter region of a second conductivity type in the semiconductor substrate on the major surface of the semiconductor substrate; a collector region of a second conductivity type in the semiconductor substrate on the major surface of the semiconductor substrate, spaced from and surrounding the emitter region, and including sides and corners; an electrically insulating layer on the major surface of the semiconductor substrate and including a first penetrating hole extending to the collector region except at a first of the corners and a second penetrating hole extending to the emitter region; a collector electrode contacting the collector region through the first penetrating hole and surrounding the emitter region except at the first corner; an emitter electrode at the same level as the collector electrode and contacting the emitter region through the second penetrating hole; and an emitter wiring layer at the same level as the emitter electrode, disposed on the insulating layer, and extending from the emitter electrode across the first corner.

    摘要翻译: 横向晶体管包括具有主表面的第一导电类型的半导体衬底; 在半导体衬底的主表面上的第二导电类型的发射极区域; 在半导体衬底的主表面上的半导体衬底中的与发射极区隔开并包围发射极区域的第二导电类型的集电极区域,并且包括侧面和角部; 在半导体衬底的主表面上的电绝缘层,并且包括延伸到第一角部处的集电极区域的第一穿透孔和延伸到发射极区域的第二穿透孔; 集电极,其通过所述第一穿透孔与所述集电极区域接合,并围绕除了所述第一拐角处的所述发射极区域; 与集电极电极相同的发射极电极,并通过第二穿透孔与发射极区域接触; 以及与发射极电极相同水平的发射极布线层,设置在绝缘层上,并从发射电极穿过第一角延伸。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号:US06972475B2

    公开(公告)日:2005-12-06

    申请号:US10687912

    申请日:2003-10-20

    申请人: Takahiro Yashita

    发明人: Takahiro Yashita

    摘要: A semiconductor device includes an N channel MOS transistor. The N channel MOS transistor includes a first P type buried layer that isolates an N epitaxial region on a P type substrate (P-SUB) from another N epitaxial region, a drain in an N well in the N epitaxial region, a source in a P well surrounding sides of the N well to isolate the N well, and a gate on upper layer portions of the drain and the source. The MOS transistor also includes a second P type buried layer between the N well and the P well and the substrate and contiguous to the P well, and an N buried layer contiguous to the P type buried layer and the P-SUB. The N epitaxial region, the P-SUB, and the first P type buried layer are connected to ground potential.

    摘要翻译: 半导体器件包括N沟道MOS晶体管。 N沟道MOS晶体管包括:第一P型掩埋层,其从另一N外延区域隔离P型衬底(P-SUB)上的N外延区域,在N外延区域中的N阱中的漏极, P井围绕N井,以隔离N井,以及排水沟和源的上层部分的闸门。 MOS晶体管还包括在N阱和P阱之间的第二P型掩埋层和与P阱邻接的衬底,以及与P型掩埋层和P-SUB邻接的N埋层。 N外延区域,P-SUB和第一P型掩埋层连接到地电位。

    Lateral transistor
    7.
    发明授权
    Lateral transistor 失效
    横向晶体管

    公开(公告)号:US5783855A

    公开(公告)日:1998-07-21

    申请号:US577373

    申请日:1995-12-22

    CPC分类号: H01L29/735

    摘要: A lateral transistor includes a first conductivity type semiconductor substrate, a first second conductivity type region in the substrate, a second second conductivity type region in the substrate spaced from and partially surrounding the first region including a plurality of sides and corners; an electrically insulating film covering the semiconductor substrate and including respective penetrating holes extending to the first and second regions; a first metal film disposed on the insulating film and contacting the second region through a first of the penetrating holes; and a second metal film disposed on the insulating film and contacting the first region through a second of the penetrating holes wherein the first metal film is missing opposite a first of the corners of the second region and the second metal film extends across the second region at the first corner.

    摘要翻译: 横向晶体管包括第一导电类型半导体衬底,衬底中的第一第二导电类型区域,衬底中的第二第二导电类型区域,其间隔开并部分地围绕包括多个侧面和拐角的第一区域; 覆盖半导体衬底并包括延伸到第一和第二区域的相应穿透孔的电绝缘膜; 第一金属膜,设置在绝缘膜上并通过第一穿透孔与第二区域接触; 以及第二金属膜,其设置在所述绝缘膜上并且穿过所述第二穿透孔与所述第一区域接触,其中所述第一金属膜与所述第二区域的第一角部相对地缺失,并且所述第二金属膜延伸穿过所述第二区域 第一个角落

    Motor driving circuit for a three-phase brushless motor
    8.
    发明授权
    Motor driving circuit for a three-phase brushless motor 失效
    三相无刷电机的电机驱动电路

    公开(公告)号:US5874817A

    公开(公告)日:1999-02-23

    申请号:US729504

    申请日:1996-10-11

    CPC分类号: G11B19/26 G11B19/22

    摘要: A switching signal generator outputs a switching signal which indicates either an accelerating mode or a decelerating mode by comparing a motor control signal and reference voltage. A first activation signal generator and a second activation signal generator output a first activation signal and a second activation signal, respectively, according to the switching signal from the switching signal generator. A switching control signal generator outputs either a switching control signal based on a motor location signal or a desired electric potential according to the switching signal from switching signal generator, a first activation signal from the first activation signal generator and a motor location signal. When a power-supply side controller and an earth side controller are in a decelerating mode, power-supply side first, second, and third output transistors are non-conductive and first second and third earth side output transistors are conductive by supplying a base current based on a predetermined electric potential from the switching control signal generator.

    摘要翻译: 开关信号发生器通过比较电机控制信号和参考电压来输出指示加速模式或减速模式的切换信号。 第一激活信号发生器和第二激活信号发生器分别根据来自切换信号发生器的切换信号输出第一激活信号和第二激活信号。 切换控制信号发生器根据来自切换信号发生器的切换信号,来自第一启动信号发生器的第一启动信号和马达位置信号,输出基于马达位置信号或期望电位的切换控制信号。 当电源侧控制器和接地侧控制器处于减速模式时,电源侧第一,第二和第三输出晶体管是非导通的,并且第一和第三和第三接地侧输出晶体管通过提供基极电流而导通 基于来自开关控制信号发生器的预定电位。

    Semiconductor device for a motor driving circuit
    9.
    发明授权
    Semiconductor device for a motor driving circuit 失效
    用于电动机驱动电路的半导体装置

    公开(公告)号:US5753964A

    公开(公告)日:1998-05-19

    申请号:US731466

    申请日:1996-10-15

    CPC分类号: H01L21/761

    摘要: A semiconductor integrated circuit device for driving a motor and including a p-type semiconductor substrate having spaced apart first and second areas; power transistors in the semiconductor substrate within the first area; a small signal system circuit in the semiconductor substrate within the second area; and an n-type isolating region in the semiconductor substrate separated from the first and second areas and disposed at least partially between the first and second areas, the n-type isolating region being connected to ground.

    摘要翻译: 一种用于驱动电动机并包括具有间隔开的第一和第二区域的p型半导体衬底的半导体集成电路器件; 第一区域内的半导体衬底中的功率晶体管; 第二区域内的半导体衬底中的小信号系统电路; 以及所述半导体衬底中的与所述第一和第二区域分离并且至少部分地设置在所述第一和第二区域之间的n型隔离区域,所述n型隔离区域与地连接。