利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.025 秒)

    Nonvolatile memory
    2.
    发明申请
    Nonvolatile memory 有权

    公开(公告)号：US20060120198A1

    公开(公告)日：2006-06-08

    申请号：US11336887

    申请日：2006-01-23

    申请人： Kazuaki Kubo

    发明人： Kazuaki Kubo

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C16/30

    摘要： There is provided a non-volatile memory capable of being supplied with two varieties of externally supplied voltages, stabilizing the operation thereof, at a voltage in the vicinity of a threshold voltage for switching over between the externally supplied voltages, and stabilizing the operation thereof, at the times of writing and erasing, respectively. The non-volatile memory comprises a power supply circuit incorporating a hysteresis comparator having two voltage levels for the threshold voltage, wherein by detection of 2.3V at a time when an externally supplied voltage rises, a detection signal goes to an “H” level, whereupon an internal step-down circuit, made up of a constant voltage circuit, and so forth, comes into action, generating an internal operation voltage at 2.2V to be subsequently supplied, and thereafter, by detection of 2.1V, the detection signal goes to an “L” level, whereupon the externally supplied voltage, as it is, is supplied as the internal operation voltage. Accordingly, since the detection signal remains in the “H” condition even when the externally supplied voltage is unstable in the vicinity of 2.3V, the internal operation voltage does not undergo variation.

    Semiconductor device and manufacturing method thereof
    3.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US06306709B1

    公开(公告)日：2001-10-23

    申请号：US09270648

    申请日：1999-03-16

    申请人： Masanori Miyagi ,  Haruo Konishi ,  Kazuaki Kubo ,  Yoshikazu Kojima ,  Toru Shimizu ,  Yutaka Saitoh ,  Toru Machida ,  Tetsuya Kaneko

    发明人： Masanori Miyagi ,  Haruo Konishi ,  Kazuaki Kubo ,  Yoshikazu Kojima ,  Toru Shimizu ,  Yutaka Saitoh ,  Toru Machida ,  Tetsuya Kaneko

    IPC分类号： H01L21336

    CPC分类号： H01L29/78696 ,  H01L21/3226 ,  H01L21/823462 ,  H01L27/0705 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/66757

    摘要： In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region 104 having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region 105 having a second impurity concentration determined by doping an impurity to the region selected by a pattern 106 of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region 104 having the first impurity concentration and the channel region 105 having the second impurity concentration are divided into a plurality of plane shapes. The channel region of the same MOSFET may be structured by the plurality of plane shapes having the plurality of impurity concentrations as described above and a threshold voltage of the MOSFET may be readily set to a desired value in response to a plane area ratio of the area having the first impurity concentration and the area having the second impurity concentration, allowing to realize a high performance semiconductor integrated circuit device at low cost.

    摘要翻译： 在MISFET中，在MISFET的沟道区域中设置沟道区域的沟道表面被第一栅极电压反转的区域和沟道表面由第二栅极电压反转的区域，作为其组成。 具有由P型半导体衬底的表面浓度确定的第一杂质浓度的通道区域104和通过掺杂杂质确定的第二杂质浓度的沟道区域105，所述沟道区域105由用于掺杂杂质的掩模的图案106选择的区域 通过离子注入等设置在P型半导体衬底上的N型MOSFET的沟道区中。 具有第一杂质浓度的沟道区域104和具有第二杂质浓度的沟道区域105被分成多个平面形状。 相同MOSFET的沟道区域可以由具有如上所述的多个杂质浓度的多个平面形状构成，并且可以根据区域的平面面积比容易地将MOSFET的阈值电压设置为期望值 具有第一杂质浓度和具有第二杂质浓度的面积，从而以低成本实现高性能半导体集成电路器件。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20110260776A1

    公开(公告)日：2011-10-27

    申请号：US13178933

    申请日：2011-07-08

    申请人： KAZUYOSHI TAKAI ,  Takahiro Yashita ,  Kikuo Kato ,  Kazuaki Kubo

    发明人： KAZUYOSHI TAKAI ,  Takahiro Yashita ,  Kikuo Kato ,  Kazuaki Kubo

    IPC分类号： H03K17/687

    CPC分类号： H03K17/6874 ,  H02M3/07 ,  H02M2003/072 ,  H03K17/063 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/625 ,  Y10T307/76

    摘要： In a power phase period when in normal operation, switch portions SW2H and SW2L and switch portions SW3H and SW3L are turned ON, respectively, and switch portions SW1H and SW1L are turned OFF. And floating power supply is provided from an electrostatic capacitance element CS to buses A and B, a floating control circuit 4, a transmitter circuit 5, and a receiver circuit 6, respectively. In a data phase period, the switch portions SW1H and SW1L are turned ON, and the switch portions SW2H, SW2L, SW3H, and SW3L are turned OFF. By that manner, the electrostatic capacitance element CS is charged by the power supply of a battery B, and an electrostatic capacitance element CH provides the floating power supply to the floating control circuit 4, the transmitter circuit 5, and the receiver circuit 6, respectively. By this manner, a floating switch unit 7 in which the number of the switch portions is considerably reduced can be configured.

    摘要翻译： 在通常动作的电力相位期间，开关部SW2H，SW2L和开关部SW3H，SW3L分别导通，开关部SW1H，SW1L分别断开。 并且浮动电源分别从静电电容元件CS提供给总线A和B，浮动控制电路4，发送器电路5和接收器电路6。 在数据相位期间，开关部分SW1H和SW1L导通，开关部分SW2H，SW2L，SW3H和SW3L截止。 通过这种方式，静电电容元件CS由电池B的电源充电，并且静电电容元件CH分别向浮动控制电路4，发送器电路5和接收器电路6提供浮动电源 。 通过这种方式，可以构成开关部分的数目明显减少的浮动开关单元7。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    5.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
    半导体集成电路设备

    公开(公告)号：US20090200874A1

    公开(公告)日：2009-08-13

    申请号：US12306500

    申请日：2006-06-30

    申请人： Kazuyoshi Takai ,  Takahiro Yashita ,  Kikuo Kato ,  Kazuaki Kubo

    发明人： Kazuyoshi Takai ,  Takahiro Yashita ,  Kikuo Kato ,  Kazuaki Kubo

    IPC分类号： H02M3/06

    CPC分类号： H03K17/6874 ,  H02M3/07 ,  H02M2003/072 ,  H03K17/063 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/625 ,  Y10T307/76

    摘要： In a power phase period when in normal operation, switch portions SW2H and SW2L and switch portions SW3H and SW3L are turned ON, respectively, and switch portions SW1H and SW1L are turned OFF. And floating power supply is provided from an electrostatic capacitance element CS to buses A and B, a floating control circuit 4, a transmitter circuit 5, and a receiver circuit 6, respectively. In a data phase period, the switch portions SW1H and SW1L are turned ON, and the switch portions SW2H, SW2L, SW3H, and SW3L are turned OFF. By that manner, the electrostatic capacitance element CS is charged by the power supply of a battery B, and an electrostatic capacitance element CH provides the floating power supply to the floating control circuit 4, the transmitter circuit 5, and the receiver circuit 6, respectively. By this manner, a floating switch unit 7 in which the number of the switch portions is considerably reduced can be configured.

    摘要翻译： 在通常动作的电力相位期间，开关部SW2H，SW2L和开关部SW3H，SW3L分别导通，开关部SW1H，SW1L分别断开。 并且浮动电源分别从静电电容元件CS提供给总线A和B，浮动控制电路4，发送器电路5和接收器电路6。 在数据相位期间，开关部分SW1H和SW1L导通，开关部分SW2H，SW2L，SW3H和SW3L截止。 由此，通过电池B的电源对静电电容元件CS进行充电，静电电容元件CH分别向浮动控制电路4，发送电路5和接收电路6提供浮动电源 。 通过这种方式，可以构成开关部分的数目明显减少的浮动开关单元7。

    Semiconductor device and manufacturing method thereof
    6.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US06498376B1

    公开(公告)日：2002-12-24

    申请号：US08459831

    申请日：1995-06-02

    申请人： Masanori Miyagi ,  Haruo Konishi ,  Kazuaki Kubo ,  Yoshikazu Kojima ,  Toru Shimizu ,  Yutaka Saitoh ,  Toru Machida ,  Tetsuya Kaneko

    发明人： Masanori Miyagi ,  Haruo Konishi ,  Kazuaki Kubo ,  Yoshikazu Kojima ,  Toru Shimizu ,  Yutaka Saitoh ,  Toru Machida ,  Tetsuya Kaneko

    IPC分类号： H01L2976

    CPC分类号： H01L29/78696 ,  H01L21/3226 ,  H01L21/823462 ,  H01L27/0705 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/66757

    摘要： A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.

    摘要翻译： MISFET设置有分段通道，该分段通道包括其中通道被第一栅极电压反相的区域和通道以第二栅极电压反相的区域。 MISFET形成在具有第一导电类型的半导体衬底中，沟道的第一反相区域具有由衬底的表面浓度确定的第一杂质浓度。 通道的第二反转区域具有通过将杂质掺杂到通过光刻工艺选择的区域而确定的第二杂质浓度。 第一反转区域和第二反转区域可以被划分成多个平面形状，并且根据第一和第二反转区域的平面面积比将MISFET的阈值电压设置为期望值。

    Power module substrate
    7.
    发明授权
    Power module substrate 有权
    电源模块基板

    公开(公告)号：US06310775B1

    公开(公告)日：2001-10-30

    申请号：US09531489

    申请日：2000-03-20

    申请人： Yoshiyuki Nagatomo ,  Toshiyuki Nagase ,  Kazuaki Kubo ,  Shoichi Shimamura

    发明人： Yoshiyuki Nagatomo ,  Toshiyuki Nagase ,  Kazuaki Kubo ,  Shoichi Shimamura

    IPC分类号： H05K720

    CPC分类号： H05K1/0271 ,  C04B2237/407 ,  H01L23/3735 ,  H01L2224/32225 ,  H05K1/0306 ,  H05K3/0061 ,  H05K2201/0355 ,  H05K2201/068 ,  Y10S428/901

    摘要： The present invention for solving the problem of suppressing the load caused by heat stress applied on an insulation substrate, reducing the manufacturing coat of a power module substrate, and improving productivity provides a power module substrate in which a buffer layer having a surface area one to three times as large as the surface area of the insulation substrate is laminated and bonded between the insulation substrate and the heat sink, wherein the buffer layer is formed using a material having a thermal expansion coefficient between the thermal expansion coefficients of the insulation substrate and the heat sink, the insulation substrate being preferably formed using AlN, Si3N4 or Al2O3, the buffer layer being preferably formed using AlSiC, and a carbon plate or a composite material of AlC, besides the thickness of the buffer layer being preferably 1.5 to 50 times as large as the thickness of the insulation substrate, and the insulation substrate, the buffer layer and the heat sink being preferably laminated via a brazing foil by bonding.

    摘要翻译： 本发明解决了由施加在绝缘基板上的热应力引起的负载的抑制问题，降低功率模块基板的制造涂层以及提高生产率的本发明提供了一种功率模块用基板，其中，缓冲层的表面积为1〜 将绝缘基板的表面积的3倍层叠并结合在绝缘基板和散热片之间，其中缓冲层使用具有绝热基板的热膨胀系数和 散热器，优选使用AlN，Si 3 N 4或Al 2 O 3形成绝缘基板，缓冲层优选使用AlSiC形成，并且碳板或AlC的复合材料除了缓冲层的厚度之外优选为1.5〜50倍 绝缘基板的厚度大，绝缘基板，缓冲层和热量大 水槽优选通过粘合通过钎焊箔层压。