公开(公告)号：US20240302997A1

公开(公告)日：2024-09-12

申请号：US18594070

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Konosuke WATANABE ,  Shinji YONEZAWA ,  Eiji SUKIGARA ,  Mitsusato HARA ,  Haruka MORI ,  Hajime YAMAZAKI

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0688

Abstract: According to one embodiment, a memory system includes a plurality of nonvolatile memory chips and a controller. The controller manages whether each of the nonvolatile memory chips is in a busy state or not. When one or more requests issued by a host are stored in at least one queue of the host, the controller identifies, from the one or more requests, a first request for a first nonvolatile memory chip that is not in the busy state. The controller executes a process in accordance with the identified first request.

公开(公告)号：US20240069747A1

公开(公告)日：2024-02-29

申请号：US18176450

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Konosuke WATANABE ,  Hajime YAMAZAKI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory controller of a memory system classifies input and output commands issued by a host into a group of read commands and a group of write commands, and manages the group of read commands and the group of write commands using first and second queues, respectively. The controller continuously processes a first group of commands among the group of read commands and the group of write commands until a first time period has elapsed from a start of the continuous processing of the first group of commands. In response to the first time period having elapsed, the controller switches a process target from the first group of commands to a second group of commands that is different from the first group of commands and selected among the group of read commands and the group of write commands.

公开(公告)号：US20210064524A1

公开(公告)日：2021-03-04

申请号：US16806173

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Keiri NAKANISHI ,  Konosuke WATANABE ,  Kohei OIKAWA ,  Daisuke IWAI

IPC: G06F12/02 ,  G06F13/16 ,  G11C16/34 ,  G11C16/10

Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.