公开(公告)号：US20230291418A1

公开(公告)日：2023-09-14

申请号：US17939692

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Masato SUMIYOSHI ,  Takashi TAKEMOTO ,  Keiri NAKANISHI

IPC: H03M7/40 ,  H03M7/30

CPC classification number: H03M7/405 ,  H03M7/6005

Abstract: According to one embodiment, a data decompression device decodes a code included in compressed data into a symbol. The data decompression device includes a first code length generation unit and a second code length generation unit. The first code length generation unit generates a first code length of a first code included in the compressed data by arithmetic calculation. The second code length generation unit generates a second code length of a second code by using a table. The second code is included in the compressed data. The second code is subsequent to the first code. The table indicates at least the first code and the second code length that is associated with the first code.

公开(公告)号：US20230283294A1

公开(公告)日：2023-09-07

申请号：US17941376

申请日：2022-09-09

Applicant: Kioxia Corporation

Inventor： Youhei FUKAZAWA ,  Keiri NAKANISHI ,  Sho KODAMA

IPC: H03M7/30 ,  H03M7/46

CPC classification number: H03M7/3088 ,  H03M7/46

Abstract: According to one embodiment, an information processing apparatus includes a processor. The processor divides teacher data into character strings, calculates a score of each of the character strings based on at least an appearance frequency of each character string in the character strings, an appearance position of each of the character string in the character strings, and a length of each of the character strings, and determines a position of each of the character strings in a preset dictionary based on the score.

公开(公告)号：US20230142767A1

公开(公告)日：2023-05-11

申请号：US17903636

申请日：2022-09-06

Applicant: Kioxia Corporation

Inventor： Keiri NAKANISHI ,  Kensaku YAMAGUCHI ,  Takashi TAKEMOTO

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, a controller of a memory system manages a first table maintaining a relationship between a logical address and a physical address, compresses first data corresponding to a first address of a write command, specifies a size of second data obtained by compressing the first data, determines allocation of the second data on a memory based on the size of the second data, stores a second address corresponding to a physical area where a head of the second data is stored and a physical area number used to store the second data in an entry of the first logical address in the first table, and stores the first address, offset of a position of a leader of the second data in the physical area, and the size of the second data in the physical area.

公开(公告)号：US20210289217A1

公开(公告)日：2021-09-16

申请号：US17019941

申请日：2020-09-14

Applicant: Kioxia Corporation

Inventor： Daisuke YASHIMA ,  Masato SUMIYOSHI ,  Keiri NAKANISHI ,  Takashi MIURA ,  Kohei OIKAWA ,  Sho KODAMA ,  Youhei FUKAZAWA ,  Zheye WANG

IPC: H04N19/423 ,  H04N19/13 ,  H04N19/146

Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.

公开(公告)号：US20240311003A1

公开(公告)日：2024-09-19

申请号：US18599914

申请日：2024-03-08

Applicant: Kioxia Corporation

Inventor： Kohei OIKAWA ,  Youhei FUKAZAWA ,  Keiri NAKANISHI ,  Sho Kodama ,  Takashi TAKEMOTO

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0673

Abstract: According to one embodiment, a memory controller includes a parameter table having entries which respectively correspond to superblock address ranges. The memory controller translates a logical address of data to be written to the memory into a superblock address, calculates compression parameters which correspond to items of data to be written to superblock addresses, writes the compression parameters to the parameter table, and compress data using the parameter table.

公开(公告)号：US20240106459A1

公开(公告)日：2024-03-28

申请号：US18208745

申请日：2023-06-12

Applicant: Kioxia Corporation

Inventor： Youhei FUKAZAWA ,  Sho KODAMA ,  Keiri NAKANISHI

IPC: H03M7/30

CPC classification number: H03M7/3084 ,  H03M7/3066

Abstract: According to one embodiment, a compression device includes a substring generator and a match information generator. The substring generator receives generates substrings which are stored in a memory. Byte positions of the substrings are different from each other. The match information generator determines a first string, at least part thereof matching at least part of one of the substrings, and outputs match information. The match information includes a position of the memory storing the first string and a length of the at least part of the first string matching the at least part of one of the substrings.

公开(公告)号：US20240031588A1

公开(公告)日：2024-01-25

申请号：US18479521

申请日：2023-10-02

Applicant: KIOXIA CORPORATION

Inventor： Daisuke YASHIMA ,  Masato SUMIYOSHI ,  Keiri NAKANISHI ,  Takashi MIURA ,  Kohei OIKAWA ,  Sho KODAMA ,  Youhei FUKAZAWA ,  Zheye WANG

IPC: H04N19/423 ,  H04N19/146 ,  H04N19/13

CPC classification number: H04N19/423 ,  H04N19/146 ,  H04N19/13 ,  H04N19/184

Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.

公开(公告)号：US20230006689A1

公开(公告)日：2023-01-05

申请号：US17688368

申请日：2022-03-07

Applicant: Kioxia Corporation

Inventor： Masato SUMIYOSHI ,  Keiri NAKANISHI ,  Kohei OIKAWA ,  Sho KODAMA

IPC: H03M7/30 ,  G06F3/06

Abstract: According to one embodiment, an interleaving unit divides a symbol string into first and second symbols. A first coding unit converts the first symbols to first codewords. A first packet generating unit generates first packets including the first codewords. A first request generating unit generates first packet requests including sizes of variable length packets. A second coding unit converts the second symbols to second codewords. A second packet generating unit generates second packets including the second codewords. A second request generating unit generates second packet requests including sizes of variable length packets. A multiplexer outputs a compressed stream including the first and second variable length packets cut out from the first and second packets.

公开(公告)号：US20210064524A1

公开(公告)日：2021-03-04

申请号：US16806173

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Keiri NAKANISHI ,  Konosuke WATANABE ,  Kohei OIKAWA ,  Daisuke IWAI

IPC: G06F12/02 ,  G06F13/16 ,  G11C16/34 ,  G11C16/10

Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.

公开(公告)号：US20250077417A1

公开(公告)日：2025-03-06

申请号：US18801968

申请日：2024-08-13

Applicant: Kioxia Corporation

Inventor： Sho KODAMA ,  Masato SUMIYOSHI ,  Keiri NAKANISHI ,  Yosei TAKASAKI

IPC: G06F12/02 ,  G11C16/04 ,  G11C16/10 ,  H03M7/40

Abstract: According to one embodiment, a variable length coding device includes circuitry. The circuitry determines N code lengths corresponding to respective N symbols, based on a Huffman tree. In a case where the N code lengths include a first code length longer than a maximum code length, the circuitry selects a first symbol corresponding to the first code length from the N symbols, selects, from the N symbols, a second symbol corresponding to a second code length shorter than the maximum code length, changes the second code length corresponding to the second symbol to a code length obtained by adding one to the second code length, and changes the first code length corresponding to the first symbol to a code length equal to the changed second code length.