公开(公告)号：US12244217B2

公开(公告)日：2025-03-04

申请号：US17475498

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Makoto Morimoto ,  Rui Ito ,  Ryuichi Fujimoto

IPC: H02M1/00 ,  H02M1/14 ,  H02M3/07

Abstract: A power supply circuit has a first node, a second node, a DC-DC converter that includes a switched capacitor, generates an output voltage based on an input voltage supplied from the first node, and outputs the output voltage from the second node, and a regulator that is connected in parallel to the DC-DC converter between the first node and the second node and controls an output current flowing to the second node based on a reference voltage lower than the input voltage.

公开(公告)号：US11100975B2

公开(公告)日：2021-08-24

申请号：US16803260

申请日：2020-02-27

Applicant: KIOXIA CORPORATION

Inventor： Rui Ito ,  Makoto Morimoto ,  Yutaka Shimizu ,  Ryuichi Fujimoto

IPC: G11C16/34 ,  G11C11/4074 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4076 ,  G11C16/04 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells connected to a word line, a circuit configured to apply a voltage to the word line, a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope, and a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.

公开(公告)号：US11183230B2

公开(公告)日：2021-11-23

申请号：US16799196

申请日：2020-02-24

Applicant: KIOXIA CORPORATION

Inventor： Rui Ito ,  Takeshi Hioka ,  Takuyo Kodama

IPC: G11C16/24 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/4094

Abstract: According to one embodiment, a sense amplifier circuit includes an amplifier having an input terminal connected to a sense node, and a first capacitor configured to be connected in a feedback path of the amplification transistor and to a bit line of a memory cell via the sense node, the first capacitor configured to supply a current to the memory cell and integrate the current when the memory cell is read.