公开(公告)号：US11520496B2

公开(公告)日：2022-12-06

申请号：US17108311

申请日：2020-12-01

Applicant: Kioxia Corporation

Inventor： Daisuke Iwai ,  Kenichiro Yoshii ,  Tetsuya Sunata

IPC: G06F3/06

Abstract: According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.

公开(公告)号：US11307797B2

公开(公告)日：2022-04-19

申请号：US16290633

申请日：2019-03-01

Applicant: Kioxia Corporation

Inventor： Tetsuya Sunata ,  Daisuke Iwai ,  Kenichiro Yoshii

IPC: G06F3/06 ,  G06F12/02

Abstract: According to one embodiment, a storage device is accessible by an external device via an interface and includes a nonvolatile memory including one or more blocks, and a controller electrically connected to the nonvolatile memory. The controller receives from the external device a request and a notification indicating that a response performance of the request is to be lowered. In response to receiving the request and notification, the controller determines a response time longer than a processing time of the request, and executes a first performance lowering process that executes a block managing process of the nonvolatile memory by using an idle time which is a difference between the response time and the processing time of the request or executes a second performance lowering process that lowers the response performance so as to process the request by spending the response time.

公开(公告)号：US11922038B2

公开(公告)日：2024-03-05

申请号：US17897071

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Takumi Fujimori ,  Tetsuya Sunata

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0652 ,  G06F3/0658 ,  G06F3/0679

Abstract: A memory system includes a nonvolatile memory including blocks, and a memory controller. The memory controller is configured to set each of the blocks to be in one of a plurality of states, including first, second, third, and fourth states. The memory controller is configured to detect a predetermined condition related to at least one of an amount of data being written into blocks in the first state and state transition of a block, upon detection of the predetermined condition, determine a maximum number of blocks to be in the fourth state based on a length of time during which each block in the fourth state has been in the fourth state, and perform an erase operation to cause one or more blocks in the third state to transition to the fourth state when a current number of blocks in the fourth state is less than the maximum number.

公开(公告)号：US11747979B2

公开(公告)日：2023-09-05

申请号：US17235144

申请日：2021-04-20

Applicant: Kioxia Corporation

Inventor： Tetsuya Sunata ,  Daisuke Iwai ,  Kenichiro Yoshii

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/2022

Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.

公开(公告)号：US11687284B2

公开(公告)日：2023-06-27

申请号：US17410789

申请日：2021-08-24

Applicant: Kioxia Corporation

Inventor： Tetsuya Sunata ,  Takumi Fujimori ,  Takahiro Kurita

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679

Abstract: A memory system includes a nonvolatile memory, a volatile memory, and a memory controller. The volatile memory includes a write buffer. The memory controller receives commands stored in a queue by a host device from the queue. The memory controller receives a command stored in a queue by the host device from the queue and, in a state where first data not satisfying a write unit is stored in the write buffer, when receiving a first command for writing the first data to the nonvolatile memory from the queue, simultaneously writes the first data and second data acquired from the host device or a predetermined region of the volatile memory different from the write buffer to the nonvolatile memory.

公开(公告)号：US11899573B2

公开(公告)日：2024-02-13

申请号：US17684576

申请日：2022-03-02

Applicant: Kioxia Corporation

Inventor： Reina Nishino ,  Tetsuya Sunata ,  Takumi Fujimori

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253

Abstract: A memory system includes a memory and a controller. The memory is configured to store a number of valid data in each of a plurality of logical blocks and a number of valid data for each of a plurality of banks in each of the logical blocks. The controller is configured to: select logical blocks of garbage collection target candidates based on the numbers of valid data in the logical blocks; calculate a maximum value among the numbers of valid data for the banks in each of the logical blocks of the garbage collection target candidates as a respective comparison value; and select one of the logical blocks of the garbage collection targets based on comparing the respective comparison values of the logical blocks of the garbage collection target candidates with each other.

公开(公告)号：US12002515B2

公开(公告)日：2024-06-04

申请号：US17686148

申请日：2022-03-03

Applicant: KIOXIA CORPORATION

Inventor： Takumi Fujimori ,  Tetsuya Sunata ,  Masanobu Shirakawa ,  Hideki Yamada

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3445

Abstract: A memory device includes a first block including a first memory cell and a first word line connected to the first memory cell, a second block including a second memory cell and a second word line connected to the second memory cell, and a control circuit. The control circuit applies a first voltage to each of the first and second word lines to supply a first erase pulse having a first erase intensity to each of the first and second blocks, when a first erase operation is executed, and applies the first voltage to the first word line and a second voltage higher than the first voltage to the second word line, to supply the first erase pulse to the first block and a second erase pulse having a second erase intensity less than the first erase intensity to the second block, when a second erase operation is executed.

公开(公告)号：US11573717B2

公开(公告)日：2023-02-07

申请号：US17201559

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Takahiro Kurita ,  Tetsuya Sunata ,  Shinichi Kanno

IPC: G06F3/06

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.