中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.014 seconds)

    Memory system including a memory controller and a memory chip that executes a two-stage program operation
    2.
    发明授权
    Memory system including a memory controller and a memory chip that executes a two-stage program operation 有权

    公开(公告)号：US11430520B2

    公开(公告)日：2022-08-30

    申请号：US16802428

    申请日：2020-02-26

    Applicant: KIOXIA CORPORATION

    Inventor： Hideki Yamada ,  Marie Takada ,  Masanobu Shirakawa

    IPC: G11C16/10 ,  G11C16/04 ,  G06F3/06 ,  G11C11/56

    Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.

    MEMORY SYSTEM
    4.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20250054564A1

    公开(公告)日：2025-02-13

    申请号：US18795818

    申请日：2024-08-06

    Applicant: Kioxia Corporation

    Inventor： Marie Takada ,  Masanobu Shirakawa ,  Naomi Takeda ,  Ryo Yamaki ,  Shogo Muto ,  Hideki Yamada

    IPC: G11C29/52 ,  G11C29/02

    Abstract: According to one embodiment, a memory system includes a memory chip and a memory controller. A first cell unit and a second cell unit are classified into a first group. A third cell unit is classified into a second group. The memory controller is configured to use a first correction amount of a read voltage when data of the first group is read and to use a second correction amount of the read voltage when data of the second group is read. When a time difference from a write operation of the first cell unit to the write operation of the second cell unit exceeds a reference value, the memory controller is configured to change a boundary position between the first group and the second group to between the first cell unit and the second cell unit, and to classify the second cell unit into the second group.

    Memory system
    6.
    发明授权
    Memory system 有权

    公开(公告)号：US11755236B2

    公开(公告)日：2023-09-12

    申请号：US17201092

    申请日：2021-03-15

    Applicant: Kioxia Corporation

    Inventor： Kengo Kurose ,  Masanobu Shirakawa ,  Naomi Takeda ,  Hideki Yamada

    IPC: G06F3/00 ,  G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

    Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.

    Memory system configured to determine a write voltage applied to memory cells based on the number of erase operations
    8.
    发明授权
    Memory system configured to determine a write voltage applied to memory cells based on the number of erase operations 有权

    公开(公告)号：US11501839B2

    公开(公告)日：2022-11-15

    申请号：US17190125

    申请日：2021-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Hideki Yamada ,  Masanobu Shirakawa

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/32

    Abstract: A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.

    Memory system
    9.
    发明授权
    Memory system 有权

    公开(公告)号：US11347584B2

    公开(公告)日：2022-05-31

    申请号：US16807220

    申请日：2020-03-03

    Applicant: Kioxia Corporation

    Inventor： Masanobu Shirakawa ,  Hideki Yamada ,  Marie Takada ,  Ryo Yamaki ,  Osamu Torii ,  Naomi Takeda

    IPC: G06F11/10 ,  G06F13/28 ,  G06F11/30 ,  G06F11/16 ,  G06F3/06 ,  G06F9/30

    Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

Patent Agency Ranking