公开(公告)号：US20250098166A1

公开(公告)日：2025-03-20

申请号：US18964178

申请日：2024-11-29

Applicant: Kioxia Corporation

Inventor： Tomoo HISHIDA ,  Yoshihisa IWATA

IPC: H10B43/27 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/18 ,  G11C8/12 ,  G11C16/04 ,  H01L23/528 ,  H01L29/792 ,  H10B43/30 ,  H10B43/50

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

公开(公告)号：US20240251561A1

公开(公告)日：2024-07-25

申请号：US18440623

申请日：2024-02-13

Applicant: Kioxia Corporation

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H10B43/35 ,  H01L21/8234 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B43/35 ,  H01L21/823437 ,  H10B43/27 ,  H10B43/50

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20230088310A1

公开(公告)日：2023-03-23

申请号：US17991694

申请日：2022-11-21

Applicant: KIOXIA CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L21/8234 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20210375923A1

公开(公告)日：2021-12-02

申请号：US17398654

申请日：2021-08-10

Applicant: Kioxia Corporation

Inventor： Tomoo HISHIDA ,  Yoshihisa IWATA

IPC: H01L27/11582 ,  G11C5/06 ,  G11C8/12 ,  G11C16/04 ,  G11C7/18 ,  G11C5/02 ,  H01L27/10 ,  H01L23/528 ,  H01L27/11575 ,  H01L29/792 ,  H01L27/11568

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.