公开(公告)号：US20230004506A1

公开(公告)日：2023-01-05

申请号：US17943798

申请日：2022-09-13

Applicant: Kioxia Corporation

Inventor： Kenji SAKAUE ,  Toshiyuki FURUSAWA ,  Shinya TAKEDA

IPC: G06F13/16 ,  G06F13/40 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G06F13/42

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

公开(公告)号：US20210406204A1

公开(公告)日：2021-12-30

申请号：US17158134

申请日：2021-01-26

Applicant: Kioxia Corporation

Inventor： Kenji SAKAUE ,  Toshiyuki FURUSAWA ,  Shinya TAKEDA

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

公开(公告)号：US20250036583A1

公开(公告)日：2025-01-30

申请号：US18917560

申请日：2024-10-16

Applicant: KIOXIA CORPORATION

Inventor： Kenji SAKAUE ,  Toshiyuki FURUSAWA ,  Shinya TAKEDA

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

公开(公告)号：US20240028529A1

公开(公告)日：2024-01-25

申请号：US18477709

申请日：2023-09-29

Applicant: KIOXIA CORPORATION

Inventor： Kenji SAKAUE ,  Toshiyuki FURUSAWA ,  Shinya TAKEDA

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: G06F13/1668 ,  G06F13/4022 ,  G06F13/4282 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/562 ,  H01L2225/06586 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.