公开(公告)号：US20210303214A1

公开(公告)日：2021-09-30

申请号：US17185104

申请日：2021-02-25

Applicant: KIOXIA CORPORATION

Inventor： Takeshi NAKANO ,  Akihiko ISHIHARA ,  Shingo TANIMOTO ,  Yasuaki NAKAZATO ,  Shinji MAEDA ,  Minoru UCHIDA ,  Kenji SAKAUE ,  Koichi INOUE ,  Yosuke KINO ,  Takumi SASAKI ,  Mikio TAKASUGI ,  Kouji SAITOU ,  Hironori NAGAI ,  Shinya TAKEDA ,  Akihito TOUHATA ,  Masaru OGAWA ,  Akira AOKI

IPC: G06F3/06 ,  G06F11/10

Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.

公开(公告)号：US20240302994A1

公开(公告)日：2024-09-12

申请号：US18589277

申请日：2024-02-27

Applicant: Kioxia Corporation

Inventor： Kenji SAKAUE ,  Yasuhiko KUROSAWA

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory system includes a nonvolatile memory, a memory controller, and a control circuit including a buffer and configured to store a first address transmitted by the memory controller in the buffer, generate a second address based on the first address stored in the buffer, and transmit the generated second address to the nonvolatile memory.

公开(公告)号：US20230004506A1

公开(公告)日：2023-01-05

申请号：US17943798

申请日：2022-09-13

Applicant: Kioxia Corporation

Inventor： Kenji SAKAUE ,  Toshiyuki FURUSAWA ,  Shinya TAKEDA

IPC: G06F13/16 ,  G06F13/40 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G06F13/42

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

公开(公告)号：US20240193080A1

公开(公告)日：2024-06-13

申请号：US18454265

申请日：2023-08-23

Applicant: Kioxia Corporation

Inventor： Noriyuki MORIYASU ,  Masaru OGAWA ,  Kenji SAKAUE

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: A memory system including a plurality of nonvolatile memories and a controller. The controller is connected to the plurality of nonvolatile memories via a plurality of channels. The nonvolatile memory stores a first parameter indicating a delay value. The controller acquires the first parameter from the nonvolatile memory. The controller delays start timing of data transfer to the nonvolatile memory via a channel among the plurality of channels by a delay value according to the first parameter.

公开(公告)号：US20240143531A1

公开(公告)日：2024-05-02

申请号：US18458249

申请日：2023-08-30

Applicant: Kioxia Corporation

Inventor： Koichi INOUE ,  Sachiyo MIYAMOTO ,  Minoru UCHIDA ,  Taro IWASHIRO ,  Kenji SAKAUE

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: A memory system includes a nonvolatile memory and a memory controller including a bus, a cache memory, a direct memory access controller, a first search circuit, a second search circuit, and a transfer control circuit. The direct memory access controller transfers cache target data stored in the nonvolatile memory to the cache memory. The second search circuit searches the cache target data that is being transferred. The transfer control circuit assigns, in response to the second search circuit detecting a search hit, to the transfer control circuit and the second search circuit, a bus right which has been assigned at least to the cache memory for the transfer of the cache target data to the cache memory, and obtains, by using the assigned bus right, a search result from the second search circuit via the bus.

公开(公告)号：US20210406204A1

公开(公告)日：2021-12-30

申请号：US17158134

申请日：2021-01-26

Applicant: Kioxia Corporation

Inventor： Kenji SAKAUE ,  Toshiyuki FURUSAWA ,  Shinya TAKEDA

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

公开(公告)号：US20220391130A1

公开(公告)日：2022-12-08

申请号：US17589583

申请日：2022-01-31

Applicant: KIOXIA CORPORATION

Inventor： Sachiyo MIYAMOTO ,  Terufumi TAKASAKI ,  Kenji SAKAUE ,  Taro IWASHIRO

IPC: G06F3/06

Abstract: A memory system includes a nonvolatile memory, and a memory controller configured to control the nonvolatile memory. The nonvolatile memory stores a busy table. The memory controller loads the busy table and controls a chip enable signal for the nonvolatile memory based on the busy table.

公开(公告)号：US20220293149A1

公开(公告)日：2022-09-15

申请号：US17470411

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Kenji SAKAUE

IPC: G11C7/22 ,  G11C7/10

Abstract: According to one embodiment, there is provided a memory system including a controller, a plurality of memory chips, and a channel. The controller outputs a clock signal, a timing control signal and a data signal. Each of the plurality of memory chips includes at least a clock input terminal, a timing control input terminal, a timing control output terminal, a data input terminal and a data output terminal. The channel includes a loop bus which connects the controller and the plurality of memory chips in a ring shape. The controller is able to control operation timings of the memory chips by transmitting the clock signal and the timing control signal to the plurality of memory chips via the channel.

公开(公告)号：US20250036583A1

公开(公告)日：2025-01-30

申请号：US18917560

申请日：2024-10-16

Applicant: KIOXIA CORPORATION

Inventor： Kenji SAKAUE ,  Toshiyuki FURUSAWA ,  Shinya TAKEDA

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

公开(公告)号：US20240061620A1

公开(公告)日：2024-02-22

申请号：US18501943

申请日：2023-11-03

Applicant: Kioxia Corporation

Inventor： Takeshi NAKANO ,  Akihiko ISHIHARA ,  Shingo TANIMOTO ,  Yasuaki NAKAZATO ,  Shinji MAEDA ,  Minoru UCHIDA ,  Kenji SAKAUE ,  Koichi INOUE ,  Yosuke KINO ,  Takumi SASAKI ,  Mikio TAKASUGI ,  Kouji SAITOU ,  Hironori NAGAI ,  Shinya TAKEDA ,  Akihito TOUHATA ,  Masaru OGAWA ,  Akira AOKI

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/1068

Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.