摘要:
The present disclosure provides an image outputting apparatus, including, an image pickup section, an error correction code calculation section adapted to calculate an error correction code using pixel data, which configure an image obtained by image pickup by the image pickup section, as an information word, and an outputting section adapted to output coded data, which are data of a codeword obtained by adding the error correction code to the pixel data, to an image processing apparatus provided in an apparatus in which the image outputting apparatus is provided.
摘要:
An image outputting apparatus includes a header production section for producing a header including header information formed from first and second frame information regarding whether pixel data included in a payload are of first and last lines of one frame, respectively, first line information regarding whether or not the pixel data included in the payload are valid, and second line information regarding a line number of a line formed from the pixel data included in the payload, and an error detection code for use for detection of an error of the header information. A packet production section produces a packet which includes, in the payload thereof, pixel data for one line which configure an image obtained by imaging by an imaging section and to which the header is added. An outputting section outputs the produced packet to an image processing apparatus.
摘要:
The present disclosure provides an image outputting apparatus, including, an image pickup section, an error correction code calculation section adapted to calculate an error correction code using pixel data, which configure an image obtained by image pickup by the image pickup section, as an information word, and an outputting section adapted to output coded data, which are data of a codeword obtained by adding the error correction code to the pixel data, to an image processing apparatus provided in an apparatus in which the image outputting apparatus is provided.
摘要:
An image outputting apparatus includes a header production section for producing a header including header information formed from first and second frame information regarding whether pixel data included in a payload are of first and last lines of one frame, respectively, first line information regarding whether or not the pixel data included in the payload are valid, and second line information regarding a line number of a line formed from the pixel data included in the payload, and an error detection code for use for detection of an error of the header information. A packet production section produces a packet which includes, in the payload thereof, pixel data for one line which configure an image obtained by imaging by an imaging section and to which the header is added. An outputting section outputs the produced packet to an image processing apparatus.
摘要:
Disclosed herein is a clock regeneration apparatus, including: an oscillator including n (an integer of two or more) gating groups connected in cascade connection to each other forming an oscillation loop, the gating groups being controlled to gate an internal clock signal with first to nth gating signals different from one another, respectively, the oscillator outputting a clock signal at least from the nth one of the gating groups; an edge detection section adapted to detect an edge of a reception data signal; a phase decision section adapted to decide a phase of the clock signal for each edge of the reception data signal and output a result of the decision as a phase decision signal; and a gating signal generation section adapted to generate the first to nth gating signals and output the gating signals to first to nth ones of the gating groups, respectively.
摘要:
Disclosed herein is a clock regeneration apparatus, including: an oscillator including n (an integer of two or more) gating groups connected in cascade connection to each other forming an oscillation loop, the gating groups being controlled to gate an internal clock signal with first to nth gating signals different from one another, respectively, the oscillator outputting a clock signal at least from the nth one of the gating groups; an edge detection section adapted to detect an edge of a reception data signal; a phase decision section adapted to decide a phase of the clock signal for each edge of the reception data signal and output a result of the decision as a phase decision signal; and a gating signal generation section adapted to generate the first to nth gating signals and output the gating signals to first to nth ones of the gating groups, respectively.
摘要:
A transmitting device includes a setting unit that sets the data length of an error correcting code whose data length is variable, an error correcting code calculator that calculates the error correcting code having the data length set by the setting unit for transmission-subject data as an information word, and a transmitting unit that transmits, to a receiving device existing in the same device, coded data that is data of a codeword obtained by adding the error correcting code obtained by calculation by the error correcting code calculator to the transmission-subject data.
摘要:
Disclosed herein is a transmission apparatus, including: an error correction code calculation section adapted to calculate an error correction code from data of a transmission object as an information word; a division section adapted to allocate coded data which configure a codeword obtained by adding the error correction code determined by the calculation by the error correction code calculation section to the data of the transmission object for each predetermined number of units to a plurality of transmission lines; and a plurality of transmission sections provided corresponding to the plural transmission lines and adapted to transmit the coded data allocated by the division section to a reception apparatus through the transmission lines.
摘要:
Disclosed herein is a synchronous oscillator including at least one injection circuit having an injection signal input terminal, an internal clock signal input terminal, and a clock output terminal, and at least one delay circuit cascaded to the injection circuit.
摘要:
Disclosed herein is a synchronous oscillator including at least one injection circuit having an injection signal input terminal, an internal clock signal input terminal, and a clock output terminal, and at least one delay circuit cascaded to the injection circuit.